Changes to Ordering Guide .......................................................... 24
3/2008—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Figure 23 ...................................................................... 14
Changes to Output Matching Section .......................................... 23
1/2008—Revision 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet
SPECIFICATIONS
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 1.
Parameter
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
REF
IN
Input Sensitivity
REF
IN
Input Capacitance
REF
IN
Input Current
PHASE DETECTOR
Phase Detector Frequency
2
CHARGE PUMP
I
CP
Sink/Source
3
High Value
Low Value
R
SET
Range
I
CP
Three-State Leakage Current
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INH
/I
INL
Input Capacitance, C
IN
LOGIC OUTPUTS
Output High Voltage, V
OH
Output High Current, I
OH
Output Low Voltage, V
OL
POWER SUPPLIES
AV
DD
DV
DD
V
VCO
AI
DD 4
DI
DD4
I
VCO4, 5
I
RFOUT4
Low Power Sleep Mode
4
RF OUTPUT CHARACTERISTICS
5
Maximum VCO Output Frequency
Minimum VCO Output Frequency
VCO Output Frequency
VCO Frequency Range
VCO Sensitivity
Lock Time
6
Frequency Pushing (Open Loop)
Frequency Pulling (Open Loop)
Harmonic Content (Second)
B Version
10/250
0.7/AV
DD
0 to AV
DD
5.0
±60
8
Unit
MHz min/MHz max
V p-p min/V p-p max
V max
pF max
µA max
MHz max
With R
SET
= 4.7 kΩ
2.5
0.312
2.7/10
0.2
2
1.5
2
1.5
0.6
±1
3.0
DV
DD
− 0.4
500
0.4
3.0/3.6
AV
DD
AV
DD
5
2.5
12.0
3.5 to 11.0
7
400
65
90/108
1.2
2
400
0.24
10
−16
mA typ
mA typ
kΩ min/kΩ max
nA typ
% typ
% typ
% typ
V min
V max
µA max
pF max
V min
µA max
V max
V min/V max
CMOS output chosen
I
OL
= 500 µA
Test Conditions/Comments
ADF4360-9
For f < 10 MHz, use a dc-coupled, CMOS-compatible
square wave, slew rate > 21 V/µs
AC-coupled
CMOS-compatible
1.25 V ≤ V
CP
≤ 2.5 V
1.25 V ≤ V
CP
≤ 2.5 V
V
CP
= 2.0 V
mA typ
mA typ
mA typ
mA typ
µA typ
MHz
MHz
MHz min/MHz max
Ratio
MHz/V typ
µs typ
MHz/V typ
Hz typ
dBc typ
Rev. D | Page 3 of 24
I
CORE
= 5 mA
RF output stage is programmable
I
CORE
= 5 mA; depending on L1 and L2; see the
Choosing the Correct Inductance Value section
L1, L2 = 270 nH; see the Choosing the Correct
Inductance Value section for other frequency values
f
MAX
/f
MIN
L1, L2 = 270 nH; see the Choosing the Correct
Inductance Value section for other sensitivity values
To within 10 Hz of final frequency
Into 2.00 VSWR load
ADF4360-9
Parameter
Harmonic Content (Third)
Output Power
5, 7
Output Power
5, 8
Output Power Variation
VCO Tuning Range
VCO NOISE CHARACTERISTICS
VCO Phase Noise Performance
9,10
B Version
−21
−9/0
−14/−9
±3
1.25/2.5
−91
−117
−139
−140
−147
−218
−110
1.4
−75
Unit
dBc typ
dBm typ
dBm typ
dB typ
V min/V max
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
ps typ
dBc typ
At 10 kHz offset from carrier
At 100 kHz offset from carrier
At 1 MHz offset from carrier
At 3 MHz offset from carrier
At 10 MHz offset from carrier
Test Conditions/Comments
Data Sheet
Using tuned load, programmable in 3 dB steps;
see Figure 35
Using 50 Ω resistors to V
VCO
, programmable in
3 dB steps; see Figure 33
Normalized In-Band Phase Noise
10, 11
In-Band Phase Noise
10, 11
RMS Integrated Jitter
12
Spurious Signals Due to PFD Frequency
13
DIVOUT CHARACTERISTICS
12
Integrated Jitter Performance
(Integrated from 100 Hz to 1 GHz)
DIVOUT = 180 MHz
DIVOUT = 95 MHz
DIVOUT = 80 MHz
DIVOUT = 52 MHz
DIVOUT = 45 MHz
DIVOUT = 10 MHz
DIVOUT Duty Cycle
A Output
A/2 Output
1
2
At 1 kHz offset from carrier
Measured at RF
OUT
A
VCO frequency = 320 MHz to 380 MHz
1.4
1.4
1.4
1.4
1.4
1.6
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
A = 2, A output selected
A = 2, A/2 output selected
A = 2, A/2 output selected
A = 3, A/2 output selected (VCO = 312 MHz,
PFD = 1.6 MHz)
A = 4, A/2 output selected
A = 18, A/2 output selected (VCO = 360 MHz,
PFD = 1.6 MHz)
Divide-by-A selected
Divide-by-A/2 selected
1/A × 100
50
% typ
% typ
Operating temperature range is −40°C to +85°C.
Guaranteed by design. Sample tested to ensure compliance.
3
I
CP
is internally modified to maintain constant loop gain over the frequency range.
4
T
A
= 25°C; AV
DD
= DV
DD
= V
VCO
= 3.3 V.
5
Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.
6
Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
For more detail on using tuned loads, see the Output Matching section.
8
Using 50 Ω resistors to V
VCO
into a 50 Ω load.
9
The noise of the VCO is measured in open-loop conditions. L1, L2 = 56 nH.
10
The phase noise is measured with the
EV-ADF4360-9EB1Z
evaluation board and the Agilent E5052A signal source analyzer.
11
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; N = 360; loop bandwidth = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of
the VCO and subtracting 20logN (where N is the N divider value) and 10logf
PFD
. PN
SYNTH
= PN
TOT
− 10logf
PFD
− 20logN.
12
The jitter is measured with the
EV-ADF4360-9EB1Z
evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REF
IN
for the
synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. f
REFIN
= 10 MHz; f
PFD
= 1 MHz; N = 360; loop bandwidth = 40 kHz, unless
otherwise noted.
13
The spurious signals are measured with the
EV-ADF4360-9EB1Z
evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides the
REF
IN
for the synthesizer; f
REFIN
= 10 MHz at 0 dBm. f
REFIN
= 10 MHz; f
PFD
= 1 MHz; N = 360; loop bandwidth = 40 kHz.
Rev. D | Page 4 of 24
Data Sheet
TIMING CHARACTERISTICS
1
ADF4360-9
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
1
Limit at T
MIN
to T
MAX
(B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Refer to the Power-Up section for the recommended power-up procedure for this device.
