1.25 Gbps Clock and Data Recovery IC
ADN2805
FEATURES
Locks to 1.25 Gbps NRZ serial data input
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
I
2
C interface to access optional features
Single-supply operation: 3.3 V
Low power: 390 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb free
GENERAL DESCRIPTION
The ADN2805 provides the receiver functions of quantization
and clock and data recovery for 1.25 Gbps. The ADN2805
automatically locks to all data rates without the need for an
external reference clock or programming. All SONET jitter
requirements are met, including jitter transfer, jitter generation,
and jitter tolerance.
All specifications are specified for −40°C to +85°C ambient
temperature, unless otherwise noted. The ADN2805 is available
in a compact 5 mm × 5 mm 32-lead LFCSP.
APPLICATIONS
GbE line card
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REFCLKN
(OPTIONAL)
LOL
CF1
CF2
VCC
VEE
FREQUENCY
DETECT
PIN
NIN
BUFFER
PHASE
SHIFTER
PHASE
DETECT
LOOP
FILTER
LOOP
FILTER
VCO
VREF
DATA
RE-TIMING
2
2
DATAOUTP/
DATAOUTN
CLKOUTP/
CLKOUTN
ADN2805
07121-001
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADN2805
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Jitter Specifications ....................................................................... 3
Output and Timing Specifications ............................................. 4
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
I
2
C Interface Timing and Internal Register Description ............. 8
Theory of Operation ...................................................................... 10
Functional Description .................................................................. 12
Frequency Acquisition ............................................................... 12
Input Buffer ................................................................................. 12
Lock Detector Operation .......................................................... 12
SQUELCH Mode........................................................................ 13
System Reset ................................................................................ 13
I
2
C Interface ................................................................................ 13
Applications Information .............................................................. 14
PCB Design Guidelines ............................................................. 14
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
1/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADN2805
SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2
23
− 1,
unless otherwise noted.
Table 1.
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
QUANTIZER—AC CHARACTERISTICS
Data Rate
S11
Input Resistance
Input Capacitance
LOSS-OF-LOCK (LOL) DETECT
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL Deassert
LOL Response Time
ACQUISITION TIME
Lock-to-Data Mode
Optional Lock to REFCLK Mode
DATA RATE READBACK ACCURACY
Fine Readback
POWER SUPPLY
Power Supply Voltage
Power Supply Current
OPERATING TEMPERATURE RANGE
Conditions
@ PIN or NIN, dc-coupled
PIN − NIN
DC-coupled
Min
1.8
0.2
2.3
Typ
Max
2.8
2.0
2.8
1250
@ 2.5 GHz
Differential
−15
100
0.65
1000
250
200
1.5
20.0
100
3.0
Locked to 1.25 Gbps
−40
3.3
118
3.6
131
+85
Unit
V
V
V
Mbps
dB
Ω
pF
ppm
ppm
μs
ms
ms
ppm
V
mA
°C
2.5
With respect to nominal
With respect to nominal
GbE
In addition to REFCLK accuracy
JITTER SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2
23
− 1,
unless otherwise noted.
Table 2.
Parameter
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Peaking
Jitter Generation
Jitter Tolerance
Conditions
Min
Typ
0
0.001
0.02
GbE, IEEE 802.3, 637 kHz
0.749
Max
0.03
0.003
0.04
Unit
dB
UI rms
UI p-p
UI p-p
Rev. 0 | Page 3 of 16
ADN2805
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
LVDS OUTPUT CHARACTERISTICS
CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN
Differential Output Swing
Output Offset Voltage
Output Impedance
LVDS Outputs Timing
Rise Time
Fall Time
Setup Time
Hold Time
2
I C® INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Output Low Voltage
I
2
C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time Between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
Input Low Voltage
Input High Voltage
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
1
Conditions
Min
Typ
Max
Unit
V
OD
(see Figure 3)
V
OS
(see Figure 3)
Differential
20% to 80%
80% to 20%
T
S
(see Figure 2), GbE
T
H
(see Figure 2), GbE
LVCMOS
V
IH
V
IL
V
IN
= 0.1 VCC or V
IN
= 0.9 VCC
V
OL
, I
OL
= 3.0 mA
See Figure 10
t
HIGH
t
LOW
t
HD;STA
t
SU;STA
t
SU;DAT
t
HD;DAT
t
R
/t
F
t
SU;STO
t
BUF
Optional lock-to-REFCLK mode
@ REFCLKP or REFCLKN
V
IL
V
IH
240
1125
300
1200
100
115
115
400
400
400
1275
mV
mV
Ω
ps
ps
ps
ps
V
V
μA
V
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
360
360
0.7 VCC
−10.0
220
220
440
440
0.3 VCC
+10.0
0.4
400
600
1300
600
600
100
300
20 + 0.1 Cb
1
600
1300
300
0
VCC
100
10
100
160
V
V
mV p-p
MHz
ppm
V
V
μA
μA
V
V
V
IH
V
IL
I
IH
, V
IN
= 2.4 V
I
IL
, V
IN
= 0.4 V
V
OH
, I
OH
= −2.0 mA
V
OL
, I
OL
= 2.0 mA
2.0
0.8
5
−5
2.4
0.4
C
b
= total capacitance of one bus line in pF. If mixed with high speed mode devices, faster fall times are allowed.
Rev. 0 | Page 4 of 16
ADN2805
Timing Characteristics
CLKOUTP
T
H
07121-002
T
S
DATAOUTP/
DATAOUTN
Figure 2. Output Timing
DIFFERENTIAL CLKOUTP/N, DATAOUTP/N
V
OH
V
OS
|V
OD
|
07121-003
V
OL
Figure 3. Differential Output Specifications
5mA
100Ω
R
LOAD
100Ω
V
DIFF
5mA
07121-004
SIMPLIFIED LVDS
OUTPUT STAGE
Figure 4. Differential Output Stage
Rev. 0 | Page 5 of 16
