EVB7122
27 to 930MHz Transceiver
Evaluation Board Description
Features
!
Single chip solution with only a few external
components
!
Stand-alone fixed-frequency user mode
!
Programmable multi-channel user mode
!
Low current consumption in active mode and
very low standby current
!
PLL-stabilized RF VCO (LO) with internal
varactor diode
!
Lock detect output in programmable
user mode
!
On-chip AFC for extended input frequency
acceptance range
!
FSK for digital data or FM for analog signal
reception
!
FSK/ASK mode selection
!
RSSI output for signal strength indication and
ASK reception
!
ASK detection normal or with peak detector
!
Switchable LNA gain for improved dynamic
range
!
Automatic PA turn-on after PLL lock
!
ASK modulation achieved by PA on/off keying
!
3wire bus serial control interface
!
EVB comes with a cable to connect to a PC’s
LPT port
!
EVB programming software is available on
Melexis web site
Ordering Information
Part No. (see paragraph 6)
EVB7122-315-FSK-C
EVB7122-433-FSK-C
EVB7122-868-FSK-C
EVB7122-915-FSK-C
Note 1:
EVB default population is FSK, ASK modifications according to section 4.2 and 4.3.
Note 2:
EVB7122 is applicable for devices TH7122 and TH71221.
Application Examples
!
General bi-directional half duplex digital data
RF signaling or analog signal communication
!
Tire Pressure Monitoring Systems (TPMS)
!
Remote Keyless Entry (RKE)
!
Low-power telemetry systems
!
Alarm and security systems
!
Wireless access control
!
Garage door openers
!
Networking solutions
!
Active RFID tags
!
Remote controls
!
Home and building automation
Evaluation Board Example
General Description
The TH7122 is a single chip FSK/FM/ASK transceiver IC. It is designed to operate in low-power multi-
channel programmable or single-channel stand-alone, half-duplex data transmission systems. It can be used
for applications in automotive, industrial-scientific-medical (ISM), short range devices (SRD) or similar
applications operating in the frequency range of 300 MHz to 930 MHz. In programmable user mode, the
transceiver can operate down to 27 MHz by employing an external VCO varactor diode.
39012 07122 02
Rev. 005
Page 1 of 24
EVB Description
June/07
EVB7122
27 to 930MHz Transceiver
Evaluation Board Description
Document Content
1
Theory of Operation ...................................................................................................3
1.1
1.2
1.3
1.4
1.5
General............................................................................................................................. 3
Technical Data Overview.................................................................................................. 3
Note on ASK Operation .................................................................................................... 3
Block Diagram .................................................................................................................. 4
User Mode Features ......................................................................................................... 4
2
Description of User Modes........................................................................................5
2.1
2.1.1
2.1.2
2.1.3
2.1.4
Stand-alone User Mode Operation ................................................................................... 5
Frequency Selection .................................................................................................................... 5
Operation Mode ........................................................................................................................... 5
Modulation Type .......................................................................................................................... 6
LNA Gain Mode ........................................................................................................................... 6
2.2
2.2.1
Programmable User Mode Operation............................................................................... 6
Serial Control Interface Description ............................................................................................. 6
3
Register Description ..................................................................................................7
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
Register Overview ............................................................................................................ 8
Default Register Settings for FS0, FS1........................................................................................ 8
A – word ....................................................................................................................................... 9
B – word ..................................................................................................................................... 10
C – word..................................................................................................................................... 11
D – word..................................................................................................................................... 12
4
Application Circuits .................................................................................................13
4.1
4.1.1
4.1.2
FSK Application Circuit Programmable User Mode (internal AFC option)...................... 13
Board Component Values for FSK Reception ........................................................................... 14
Component Arrangement Top Side for FSK Reception ............................................................ 15
4.2
4.2.1
4.2.2
ASK Application Circuit Programmable User Mode (normal data slicer option) ............. 16
Board Component Values for ASK (normal data slicer option) ................................................. 17
Component Arrangement Top Side for ASK Reception (normal data slicer option) ................. 18
4.3
4.3.1
4.3.2
ASK Application Circuit with Peak Detector Option ........................................................ 19
Board Component Values for ASK (peak detector option)........................................................ 20
Component Arrangement Top Side for ASK Reception (peak detector option)........................ 21
5
6
7
Evaluation Board Layouts .......................................................................................22
Board Variants..........................................................................................................22
Package Description ................................................................................................23
7.1
Soldering Information ..................................................................................................... 23
8
Disclaimer .................................................................................................................24
39012 07122 02
Rev. 005
Page 2 of 24
EVB Description
June/07
EVB7122
27 to 930MHz Transceiver
Evaluation Board Description
1
1.1
Theory of Operation
General
The main building block of the transceiver is a programmable PLL frequency synthesizer that is based on an
integer-N topology. The PLL is used for generating the carrier frequency during transmission and for
generating the LO signal during reception. The carrier frequency can be FSK-modulated by pulling the
crystal and ASK-modulated by on/off keying of the power amplifier. The receiver is based on the principle of
a single conversion superhet. Therefore the VCO frequency has to be changed between transmit and
receive mode. In receive mode, the preferred LO injection type is low-side injection.
The TH7122 transceiver IC consists of the following building blocks:
"
"
"
"
"
"
"
Low-noise amplifier (LNA) for high-sensitivity
RF signal reception with switchable gain
Mixer (MIX) for RF-to-IF down-conversion
IF amplifier (IFA) to amplify and limit the IF
signal and for RSSI generation
Phase-coincidence demodulator with external
ceramic discriminator (FSK Demodulator)
Operational amplifier (OA1), connected to
demodulator output
Operational amplifier (OA2), for geral use
Peak detector (PKDET) for ASK detection
"
"
"
"
"
"
"
"
Control logic with 3wire bus serial control
interface (SCI)
Reference oscillator (RO) with external crystal
Reference divider (R counter)
Programmable divider (N/A counter)
Phase-frequency detector (PFD)
Charge pump (CP)
Voltage controlled oscillator (VCO) with internal
varactor
Power amplifier (PA) with adjustable output
power
1.2
Technical Data Overview
!
Sensitivity: -107 dBm at ASK with 180 kHz
IF filter BW
!
Max. data rate with crystal pulling: 20 kbps NRZ
!
Max. data rate with direct VCO modulation:
115 kbps NRZ
!
Max. input level: -10 dBm at FSK
and -20 dBm at ASK
!
Input frequency acceptance:
±
10 to
±
150 kHz
(depending on FSK deviation)
!
FM/FSK deviation range:
±2.5
to
±80
kHz
!
Analog modulation frequency: max. 10 kHz
!
Crystal reference frequency: 3 MHz to 12 MHz
!
External reference frequency: 1 MHz to 16 MHz
!
Frequency range: 300 MHz to 930 MHz in
programmable user mode
!
Extended frequency range with external VCO
varactor diode: 27 MHz to 930 MHz
!
315 MHz, 433 MHz, 868 MHz or 915 MHz fixed-
frequency settings in stand-alone mode
!
Power supply range: 2.2 V to 5.5 V
!
Temperature range: -40 °C to +85 °C
!
Standby current: 50 nA
!
Operating current in receive: 6.5 mA (low gain)
!
Operating current in transmit: 12 mA (at -2 dBm)
!
Adjustable RF power range: -20 dBm to
+10dBm
!
Sensitivity: -105 dBm at FSK with 180 kHz
IF filter BW
1.3
Note on ASK Operation
Optimum ASK performance can be achieved by using an 8-MHz crystal for operation at 315 MHz, 434 MHz
and 915 MHz. For details please refer to the software settings shown in sections 4.2 and 4.3. FSK operation
is the preferred choice for applications in the European 868MHz band.
For more detailed information, please refer to the latest TH7122 data sheet revision
39012 07122 02
Rev. 005
Page 3 of 24
EVB Description
June/07
EVB7122
27 to 930MHz Transceiver
Evaluation Board Description
1.4
Block Diagram
GAIN_LNA
OUT_LNA
VEE_LNA
IN_MIX
VEE_IF
OUT_MIX
VCC_IF
IN_IFA
RSSI
27
29
28
30
32
31
1
2
7
3
IN_DEM
6
OUT_DEM
PKDET
SW1
1.5pF
bias
OA2
4
FSK Demodulator
MIX
SW2
200k
INT2/PDO
5
IN_LNA
26
MIX
LNA
LO
IF
INT1
IFA
OA1
8
OUT_DTA
Control Logic
ASK
SCI
SDEN
SDTA
SCLK
N
counter
VCO
R
counter
RO
RO
FSK_SW
FSK
FS0/SDEN
OUT_PA
25
PA
ASK/FSK
RE/SCLK
VEE_RO
24
PS_PA
21
TNK_LO
20
VCC_PLL
23
LF
22
VEE_PLL
10
RO
FS1/LD
11
19
9
12
13
15
16
17
18
14
Fig. 1:
TH7122 block diagram
1.5
User Mode Features
The transceiver can operate in two different user modes. It can be used either as a 3wire-bus-controlled
programmable or as a stand-alone fixed-frequency device. After power up, the transceiver is set to Stand-
alone User Mode (SUM). In this mode, pins FS0/SDEN and FS1/LD must be connected to V
EE
or V
CC
in
order to set the desired frequency of operation. There are 4 pre-defined frequency settings: 315MHz,
433.92MHz, 868.3MHz and 915MHz. The logic level at pin FS0/SDEN must not be changed after power up
in order to remain in fixed-frequency mode.
After the first logic level change at pin FS0/SDEN, the transceiver enters into Programmable User Mode
(PUM). In this mode, the user can set any PLL frequency or mode of operation by the SCI. In SUM pins
FS0/SDEN and FS1/LD are used to set the desired frequency, while in PUM pin FS0/SDEN is part of the
3-wire serial control interface (SCI) and pin FS1/LD is the look detector output signal of the PLL synthesizer.
A mode control logic allows several operating modes. In addition to standby, transmit and receive mode, two
idle modes can be selected to run either the reference oscillator only or the whole PLL synthesizer. The PLL
settings for the PLL idle mode are taken over from the last operating mode which can be either receive or
transmit mode.
The different operating modes can be set in SUM and PUM as well. In SUM the user can program the
transceiver via control pins RE/SCLK and TE/SDTA. In PUM the register bits OPMODE are used to select
the modes of operation while pins RE/SCLK and TE/SDTA are part of the SCI.
39012 07122 02
Rev. 005
Page 4 of 24
EVB Description
June/07
VCC_DIG
VEE_DIG
TE/SDTA
IN_DTA
EVB7122
27 to 930MHz Transceiver
Evaluation Board Description
2
2.1
Description of User Modes
Stand-alone User Mode Operation
After power up the transceiver is set to stand-alone user mode. In this mode, pins FS0/SDEN and FS1/LD
must be connected to V
EE
or V
CC
to set the desired frequency of operation. The logic level at pin FS0/SDEN
must not be changed after power up in order to remain in stand-alone user mode. The default settings of the
control word bits in stand-alone user mode are described in the frequency selection table. Detailed
information about the default settings can be found in the tables of section 5.
2.1.1
Frequency Selection
Channel frequency
433.92 MHz
1
0
868.3 MHz
0
0
7.1505 MHz
32
223.45 kHz
1894
423.22 MHz
433.92 MHz
32
223.45 kHz
1942
433.92 MHz
433.92 MHz
10.7 MHz
16
446.91 kHz
1919
857.60 MHz
868.30 MHz
16
446.91 kHz
1943
868.30 MHz
868.30 MHz
10.7 MHz
18
397.25 kHz
766
304.30 MHz
315.00 MHz
18
397.25 kHz
793
315.00 MHz
315.00 MHz
10.7 MHz
32
223.45 kHz
4047
904.30 MHz
915.00 MHz
32
223.45 kHz
4095
915.00 MHz
915.00 MHz
10.7 MHz
315 MHz
1
1
915 MHz
0
1
FS0/SDEN
FS1/LD
Reference oscillator frequency
R counter ratio in RX mode (RR)
PFD frequency in RX mode
N counter ratio in RX mode (NR)
VCO frequency in RX mode
RX frequency
R counter ratio in TX mode (RT)
PFD frequency in TX mode
N counter ratio in TX mode (NT)
VCO frequency in TX mode
TX frequency
IF in RX mode
In stand-alone user mode, the transceiver can be set to Standby, Receive, Transmit or Idle mode (only PLL
synthesizer active) via control pins RE/SCLK and TE/SDTA. The modulation scheme and the LNA gain are
set by pins ASK/FSK and GAIN_LNA, respectively.
2.1.2
Operation Mode
Operation mode
RE/SCLK
TE/SDTA
Standby
0
0
Receive
1
0
Transmit
0
1
Idle
1
1
Note:
Pins with internal pull-down
39012 07122 02
Rev. 005
Page 5 of 24
EVB Description
June/07
微控制器 MCU
