v3.0
eX Family FPGAs
Le a di n g E d ge P er f o r m a n ce
• 240 MHz System Performance
• 3.9ns Clock-to-Out (Pad-to-Pad)
• 350 MHz Internal Performance
Sp e ci f i c a t i on s
• Individual Output Slew Rate Control
• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V
Input Tolerance and 5.0V Drive Strength
• Software Design Support with Actel Designer Series and
Libero Tools
• Up to 100% Resource Utilization with 100% Pin Locking
• Deterministic Timing
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
G en er al D e sc r i p t i on
• 3,000 to 12,000 Available System Gates
• As Many as 512 Maximum Flip-Flops (Using CC Macros)
• 0.22
µ
CMOS Process Technology
• Up to 132 User-Programmable I/O Pins
Fe a t ur es
• High-Performance, Low-Power Antifuse FPGA
• LP/Sleep Mode for Additional Power Savings
• Advanced Small-footprint Packages
• Hot-Swap Compliant I/Os
• Single-Chip Solution
• Nonvolatile
• Live on power up
• Power-Up/Down Friendly (No Sequencing Required for
Supply Voltages)
• Configurable Weak-Resistor Pull-Up or Pull-Down for
Tristated Outputs during Power Up
eX P r o du ct Pr o f i l e
Device
Capacity
System Gates
Typical Gates
Register Cells (Dedicated Flip-Flops)
Combinatorial Cells
Maximum User I/Os
Speed Grades
Temperature Grades
Package
(by pin count)
TQFP
CSP
The eX family of FPGAs is a low-cost solution for low-power,
high-performance designs. The inherent low power
attributes of the antifuse technology, coupled with an
additional low static power mode, make these devices ideal
for power-sensitive applications. Fabricated with an
advanced 0.22
µ
CMOS antifuse technology, these devices
achieve high performance with no power penalty
.
eX64
3,000
2,000
64
128
84
–F, Std, –P
C, I
64, 100
49, 128
eX128
6,000
4,000
128
256
100
–F, Std, –P
C, I
64, 100
49, 128
eX256
12,000
8,000
256
512
132
–F, Std, –P
C, I
100
128, 180
D e ce m b e r 2 0 0 1
1
© 2001 Actel Corporation
e X F a m il y F P GA s
O r d e r i n g I nf o r m a t i o n
eX128
–P
TQ
100
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
PP = Pre-production
Package Lead Count
Package Type
TQ = Thin (1.4mm) Quad Flat Pack
CS = Chip-Scale Package (0.8mm pitch)
Speed Grade
Blank = Standard Speed
–P = Approximately 30% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
eX64 =
eX128 =
eX256 =
64 Dedicated Flip-Flops (3,000 System Gates)
128 Dedicated Flip-Flops (6,000 System Gates)
256 Dedicated Flip-Flops (12,000 System Gates)
Pr od uc t P l a n
Speed Grade
–F
eX64 Device
64-Pin Thin Quad Flat Pack (TQFP)
100-Pin Thin Quad Flat Pack (TQFP)
49-Pin Chip Scale Package (CSP)
128-Pin Chip Scale Package (CSP)
eX128 Device
64-Pin Thin Quad Flat Pack (TQFP)
100-Pin Thin Quad Flat Pack (TQFP)
49-Pin Chip Scale Package (CSP)
128-Pin Chip Scale Package (CSP)
eX256 Device
100-Pin Thin Quad Flat Pack (TQFP)
✔
128-Pin Chip Scale Package (CSP)
✔
180-Pin Chip Scale Package (CSP)
✔
Contact your Actel sales representative for product availability.
Speed Grade: –P = Approx. 30% faster than Standard
Availability:
✔
=
–F = Approx. 40% slower than Standard
✔
✔
✔
Available
✔
✔
✔
Applications:
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Std
–P
Application
C
I
†
C = Commercial
I = Industrial
† Only Std Speed Grade
Pl a s t i c D e vi c e Re so u r ce s
User I/Os (including clock buffers)
Device
eX64
eX128
eX256
Package Definitions:
TQFP 64-Pin
41
46
TQFP 100-Pin
56
70
CSP 49-Pin
36
36
CSP 128-Pin
84
100
100
CSP 180-Pin
—
—
132
—
81
—
TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package
2
v3.0
e X F a m il y F P GA s
eX F am i l y A r c hi t e c t ur e
The eX family architecture uses a “sea-of-modules”
structure where the entire floor of the device is covered
with a grid of logic modules with virtually no chip area lost
to interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
patented
metal-to-metal
programmable
antifuse
interconnect elements. Actel’s eX family provides two types
of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals (Figure
1).
The R-cell registers
feature programmable clock polarity selectable on a
register-by-register basis. This provides additional flexibility
while allowing mapping of synthesized functions into the eX
FPGA. The clock source for the R-cell can be chosen from
either the hard-wired clock or the routed clock.
The C-cell implements a range of combinatorial functions
up to 5 inputs (Figure
2).
Inclusion of the DB input and its
associated inverter function dramatically increases the
number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the eX
architecture.
M o d ule O r g a n i z a t io n
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. The eX devices contain
one type of Cluster, which contains two C-cells and one
R-cell.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(Figure
3 on page 4).
The eX devices contain one type of
SuperClusters, which are two-wide groupings of one type of
clusters.
S0
Routed
Data Input S1
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CKS
CKP
CLR
Figure 1 •
R-Cell
D0
D1
Y
D2
D3
Sa
Sb
DB
A0
B0
A1
B1
Figure 2 •
C-Cell
v3.0
3
e X F a m il y F P GA s
Rou ti ng Res our ces
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure
4).
This routing
architecture also dramatically reduces the number of
antifuses required to complete a circuit, ensuring the
highest possible performance.
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns (–P speed
grade).
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.3 ns
(–P speed grade).
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100 percent
automatic place-and-route software to minimize signal
propagation delays.
R-Cell
Routed
Data Input S1
D0
D1
PSET
DirectConnect
Input
D2
D
Q
Y
D3
C-Cell
S0
Y
Sa
Sb
HCLK
CLKA,
CLKB,
Internal Logic
CKS
CKP
CLR
DB
A0
B0
A1
B1
Cluster 1
Cluster 1
Type 1 SuperCluster
Figure 3 •
Cluster Organization
Type 1 SuperClusters
DirectConnect
• No antifuses
• 0.1 ns routing delay
FastConnect
• One antifuse
• 0.3 ns routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Figure 4 •
DirectConnect and FastConnect for Type 1 SuperClusters
4
v3.0
e X F a m il y F P GA s
Cl ock Res our ce s
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-Cell.
HCLK cannot be connected to combinational logic. This
provides a fast propagation path for the clock signal,
enabling the 3.9ns clock-to-out (pad-to-pad) performance of
the eX devices. The hard-wired clock is tuned to provide a
clock skew of less than 0.1ns worst case.
The remaining two clocks (CLKA, CLKB) are global clocks
that can be sourced from external pins or from internal
logic signals within the eX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals then
the external clock pin cannot be used for any other input
and must be tied low or high.
Figure 5
describes the clock
circuit used for the constant load HCLK.
Figure 6
describes
the CLKA and CLKB circuit used in eX devices.
platform upon which to integrate the functionality
previously contained in CPLDs. In addition, designs that
previously would have required a gate array to meet
performance goals can now be integrated into an eX device
with dramatic improvements in cost and time to market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
I/O Modules
Each I/O on an eX device can be configured as an input, an
output, a tristate output, or a bidirectional pin. Even without
the inclusion of dedicated I/O registers, these I/Os, in
combination with array registers, can achieve clock-to-out
(pad-to-pad) timing as fast as 3.9ns. I/O cells that have
embedded latches and flip-flops require instantiation in HDL
code; this is a design complication not encountered in eX
FPGAs. Fast pin-to-pin timing ensures that the device will
have little trouble interfacing with any other device in the
system, which in turn enables parallel design of system
components and reduces overall design time. See
Table 1
for
more information.
Table 1 •
I/O Features
Function
Input Buffer
Threshold
Selection
Flexible
Output
Driver
Output
Buffer
Description
• TTL/3.3V LVTTL
Constant Load
Clock Network
HCLKBUF
Figure 5 •
eX HCLK Clock Pad
• 2.5V LVCMOS 2
• 3.3V LVTTL
• 5.0V TTL/CMOS
“Hot-Swap” Capability
• I/O on an unpowered device does not
sink current
• Can be used for “cold sparing”
Selectable on an individual I/O basis
Individually selectable low-slew option
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 6 •
eX Routed Clock Buffer
O t he r A r c hi t ec tu ral Fe atu r e s
T echno log y
Power Up
Individually selectable pull ups and pull
downs during power up (default is to power
up in tristate)
Enables deterministic power up of device
V
CCA
and V
CCI
can be powered in any order
Actel’s eX family is implemented on a high-voltage twin-well
CMOS process using 0.22
µ
design rules. The metal-to-metal
antifuse is made up of a combination of amorphous silicon
and dielectric material with barrier metals and has an “on”
state resistance of 25
Ω
with a capacitance of 1.0 fF for low
signal impedance.
P erf orm a nce
Hot S wa ppin g
The combination of architectural features described above
enables eX devices to operate with internal clock
frequencies exceeding 350 MHz for very fast execution of
complex logic functions. Thus, the eX family is an optimal
eX I/Os are configured to be hot swappable. During power
up/down (or partial up/down), all I/Os are tristated. V
CCA
and V
CCI
do not have to be stable during power up/down,
and they do not require a specific power-up or power-down
sequence in order to avoid damage to the eX devices. After
the eX device is plugged into an electrically active system,
the device will not degrade the reliability of or cause
damage to the host system. The device’s output pins are
driven to a high impedance state until normal chip
v3.0
5
