F71869A
Super I/O + Hardware Monitor
Release Date:October, 2011
Version: V0.19P
F71869A
F71869A Datasheet Revision History
Version
0.10P
0.11P
Date
2010/04
2010/05
Page
45, 46
47-136
Revision History
Preliminary version
1. Update CIR/CPT function description
2. Update Register
0.12P
2010/06
19
47, 48
65, 66
142-144
10-20
70
90, 91
60, 61
10
140
13, 21
56
74
129, 130
132
133
148
147
50
13, 21
8, 12, 47
0.13P
2010/07
0.14P
2010/08
52
56
58~62
59
60
61, 62
122~126
135
12-13
12-21
131
77
140
19
121
112
139-140
150
64
77
60
127
0.15P
2010/08
0.16P
2010/09
0.17P
2011/03
1. Modify pin54 description
2. Add scan code and OVT function description
3. Update RS485 enable register description
⎯
Index F0h
4. DC Characteristics
5. Update Pin Description
6. Update OVT register
⎯
Index 02h
7. Update Fan3 control register
⎯
Index 9Ah
8. Add Multi-Function Select Register 5
⎯
Index 2Ch
9. Correct Pin Type
10. Add Intel DSW Delay Select Register⎯ Index FCh
11. Update STRAP_PROTECT description
12. Update Configuration Port Select Register
⎯
Index 27h
13. Add Voltage Protection Power Good Select Register
⎯
Index 3Fh
14. Add CIR Registers (CR08)
15. Update ERP PSOUT deb-register
⎯
Index E5h;
ERP S5 Delay Register
⎯
Index E7h
16. Update ERP WDT Timer
⎯
Index EEh
17. Update Application Circuit
⎯
S5# (S4#) , SUS_ACK# (3VA)
1. Update Application Circuit – Correct VIN5 pin name
1. Update Global Control Registers
2. Modify description for STRAP_PROTECT
3. Update GPIO for Scan Code function
4. Update GPIO Device Configuration Registers (LDN CR06)
5. Update UART IRQ Sharing Register
⎯
Index 26h bit 3
6. Update Multi-Function Select Register 1 ~ 5
⎯
Index 28h ~ 2Ch
7. Add WDT Clock Divisor High Byte
⎯
Index 29h
8. Add WDT Clock Divisor Low Byte
⎯
Index 2Ah
9. Add WDT Clock Fine Tune Count
⎯
Index 2Bh, 2Ch
10. Update GPIO 35 ~ 37 Scan Code Function Registers
11. Update ERP WDT Control register
⎯
Index EDh
Update for LAB version
1. Correct FDC/GPIO PWR Type
2. Correct PWR Type VCC to 3VCC
3. Add WDT Enable Register 30h and Base Address High/Low Register
60h and 61h
4. Add 2D – 2Fh in Voltage reading and limit register
5. Remove PCIRSTIN_N in VDDOK Delay Register
⎯
Index F5h bit 2
6. Correct RSTCON# pin description
7. Update GPIO4 Drive Enable Register -Index B3h bit 5~7
8. Add Auto Swap Register - Index FEh (Powered by VBAT) bit 3
9. Correct VDDOK Delay Register - Index F5h PWROK unit
10. Update Reference Circuit – Add C58
1. Made Clarification & Modification
2. Update Wakeup Control Register - Index 2Dh bit5 description
3. Add Voltage reading and limit - Index 30h, 31h
4. Modify Multi-Function Select Register 3
⎯
Index 2Ah bit 1:0
5. Modify GPIO5 KBC Emulation Control Register 2
⎯
Index AFh bit7
2
Oct., 2011
V0.19P
description
63
18, 19
112
150, 154
17, 18
148
58
149
F71869A
6. Correct Multi-Function Select Register 5 ( Index 2Ch bit3:1
default velue
7. Modify SCL & SDA Types and Description (pin 57/58/59/60)
8. Modify Auto Swap Register ( Index FEh, bit 7
1. Made Clarification & Modification
2. Update Application Circuits
3. Update FANCTL1~3 Pin Description
4. Add Top Marking Specification
5. Update Multi-Function Select Register 1⎯ Index 28h bit7 Description
6. Update Package Dimension
1.Made Clarification & Modification
2.GPIO Pin Status Register – Index F2h, bit 5 & 4
3.Update Index no.(GPIO7 Output Data Register – Index 81h)
4.Update Index no.(GPIO7 Pin Status Register – Index 82h)
5.Update Index no.(GPIO7 Drive Enable Register – Index 83h)
6.Update Index no.(User Wakeup Code Register – Index FFh)
7.SMB Protocol Select – Index EFh, bit3-0
8.Update Top Marking Specification Description
0.18P
2011/06
0.19P
2011/10
-
Please note that all data and specifications are subject to change without notice. All the trade marks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICAT
These products are not designed for use in life support appliances, devices, or systems where malfunction of
these products can reasonably be expected to result in personal injury. Customers using or selling these
products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any
damages resulting from such improper use or sales.
3
Oct., 2011
V0.19P
F71869A
Table of Content
1. General Description...............................................................................................................6
2. Feature List ...........................................................................................................................7
3. Pin Configuration.................................................................................................................10
4. Pin Description .................................................................................................................... 11
4.1 Power Pins ................................................................................................................12
4.2 LPC Interface ............................................................................................................12
4.3 FDC ...........................................................................................................................12
4.4 UART and SIR...........................................................................................................14
4.5 Parallel Port...............................................................................................................16
4.6 Hardware Monitor ......................................................................................................17
4.7 ACPI Function Pins ...................................................................................................18
4.8 Power Saving and Others..........................................................................................20
4.9 KBC Function ............................................................................................................21
5. Function Description............................................................................................................22
5.1 Power on Strapping Option........................................................................................22
5.2 Hardware Monitor ......................................................................................................22
5.3 ACPI Function ...........................................................................................................36
5.4 Power Timing Control Sequence ...............................................................................38
5.5 S3_Gate#, S3P5_Gate# and S0P5_Gate# Timing....................................................39
5.6 AMD TSI and Intel PECI 3.0 Functions .....................................................................41
5.7 ErP Power Saving Function.......................................................................................42
5.8 CIR Function .............................................................................................................46
5.9 Intel Cougar Point Timing (CPT)................................................................................47
5.10 Scan Code Function ..................................................................................................48
5.11 Over Voltage Protection.............................................................................................48
6. Register Description ............................................................................................................49
6.1 Global Control Registers ...........................................................................................54
6.2 FDC Registers (CR00) ..............................................................................................64
6.3 UART1 Registers (CR01) ..........................................................................................67
6.4 UART2 Registers (CR02) ..........................................................................................68
6.5 Parallel Port Register (CR03) ....................................................................................69
6.6 Hardware Monitor Registers (CR04) .........................................................................70
6.7 KBC Registers (CR05) ............................................................................................ 110
6.8 GPIO Registers (CR06)........................................................................................... 111
6.9 Watch Dog Timer Registers (CR07) ........................................................................130
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Oct., 2011
V0.19P
6.10 CIR Registers (CR08)..............................................................................................132
6.11 PME, ACPI, and ERP Power Saving Registers (CR0A) ..........................................133
7. Electrical Characteristics ...................................................................................................144
7.1 Absolute Maximum Ratings.....................................................................................144
7.2 DC Characteristics ..................................................................................................144
8. Ordering Information .........................................................................................................147
9. Top Marking Specification..................................................................................................147
10.Package Dimensions (128-LQFP) ...................................................................................148
11.Application Circuit ............................................................................................................149
F71869A
5
Oct., 2011
V0.19P
