F71889E
F71889E
Super Hardware Monitor + LPC I/O
Release Date: April, 2010
Version: V0.19P
April, 2010
V0.19P
F71889E
F71889E Datasheet Revision History
Version
V0.10P
V0.11P
Date
2009/8/24
2009/8/25
Page
-
-
Preliminary Version.
Modify Pin 45~48 and Pin Configuration
Made Clarification and Correction
Switch BSGPIO_STRP from pin 5 to pin 2
Made Clarification and Correction
Made Clarification and Correction
Add VSB_CTRL2# to pin 46
Modify Section 6 Pin Description Power Type
V0.13P
2009/9/17
-
BSGPIO_TRAP: Default is GPIO (Pin 2 and Section 7.1)
Support LED blinking function at deep S3 & S5
Support PECI 3.0
Add Registers & Application Circuit
V0.14P
2009/9/21
-
Update Package from 128-PQFP to 128-LQFP
Made Clarification and Correction
Update Application Circuit & Pin Configuration
Made Clarification and Correction
Update Application Circuit & Pin Configuration (Update pin
41,42, 46, 60, 65, & 99)
V0.16P
2009/10/12
-
Update Pin Description Power Type
Update Fan Fault Time Register — Index 9Fh, bit 5
Made Clarification and Correction
V0.17P
2009/11/11
-
Made Clarification and Correction
Update Application Circuit & Pin Configuration
Revision History
V0.12P
2009/8/31
-
V0.15P
2009/9/28
-
April, 2010
V0.19P
F71889E
Made Clarification and Correction
Modify DIODE OPEN Status Register -- Index 6Fh (bit 3 & 2)
Modify LED_VSB Control Register -- Index FEh (bit 6)
Modify LED_VCC Control Register -- Index FFh (bit 6 &7)
Modify PME Event Enable 2 Register
--
Index F2h (bit 2 & 1)
Modify PME Event Status Register -- Index F1h
Modify ACPI Control Register 4 -- Index F7h
Modify RI De-bounce Select Register -- Index FEh
Modify EUP control register
--
Index E1h (bit 7-6 default value)
Modify EUP control register -- Index E2h (bit 7-6)
Modify EUP S5 deb-register -- Index E7h
Add EuP Wakeup Event Enable Register -- Index E8h
Add EuP Watchdog Control Register -- Index EDh
Add EuP Watchdog Time Register -- Index EEh
Update Chip ID – Index 20 & 21h
Modify PECI/SST/TSI Configuration Register 1
⎯
Index
01h bit 5
Modify PECI/SST/TSI Configuration Register 2
⎯
Index
V0.18P
2009/12/22
-
07h
Add Over-Voltage Protection Enable Register
⎯
Index 14h
Add Over-Voltage Protection Event Status Register
⎯
Index 15h
Modify Voltage reading and limit⎯ Index 2Ch- 4Fh
Add Fan1 Base Temperature Register – Index 94h
(FAN_PROG_SEL = 1)
Add Fan1 Temperature Adjustment Rate Register – Index
95h (FAN_PROG_SEL = 1)
Add FAN PROGRAMMABLE DUTY-CYCLE/VOLTAGE
LOADED AFTER POWER-ON
⎯
Index 9Eh
Modify FAN1 Temperature Mapping Select – Index AFh bit
1,0
Modify FAN2 Temperature Mapping Select – Index BFh bit
1,0
Modify FAN3 Temperature Mapping Select – Index BFh bit
1,0
Enhance Fan Speed Count Description
Made Clarification & Correction
V0.19P
2010/1/19
Update Voltage1 PME# Enable Register Index 10h
Voltage1 Interrupt Status Register Index 11h bit 0
April, 2010
V0.19P
F71889E
Over-Voltage Protection Enable Register Index 14h
Over-Voltage Protection Event Status Register Index 15h
Multi Function Select 1 Register Index 2Ah bit 7-6
Wakeup Control Register Index 2Dh bit 6
GPIO0 Drive Enable Register Index F3h bit 3
EUP control register Index E2
Pin 58 & 59 pin type
Add Multi Temperature Explanation
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from
such improper use or sales.
April, 2010
V0.19P
F71889E
Table of Content
General Description ........................................................................................................ 1
Feature List..................................................................................................................... 1
Key Specification ............................................................................................................ 4
Block Diagram ................................................................................................................ 4
Pin Configuration ............................................................................................................ 5
Pin Description ............................................................................................................... 6
6.1 Power Pin.................................................................................................................... 6
6.2 LPC Interface ..............................................................................................................7
6.3 UART, SIR, GPIO and 80-Port .................................................................................... 7
6.4 Parallel Port ................................................................................................................ 9
6.5 Hardware Monitor, EUP ............................................................................................ 11
6.6 ACPI Function Pins ................................................................................................... 13
6.7 Bus Interface ............................................................................................................. 14
6.8 KBC Function ............................................................................................................ 14
7.
Function Description ..................................................................................................... 15
7.1. Power on Strapping Option ....................................................................................... 15
7.2. Hardware Monitor...................................................................................................... 15
7.3. Keyboard Controller .................................................................................................. 54
7.4. 80 Port ...................................................................................................................... 56
7.5. ACPI Function ........................................................................................................... 56
7.6. PECI Function ........................................................................................................... 60
7.7. SST Function ............................................................................................................ 61
7.8. TSI Function..............................................................................................................61
7.9. FSB Bus Interface ..................................................................................................... 61
7.10. VID Controller ........................................................................................................ 61
8.
Register Description ..................................................................................................... 62
8.1 Global Control Registers ........................................................................................... 65
8.2 UART1 Registers (CR01).......................................................................................... 69
8.3 UART 2 Registers (CR02)......................................................................................... 70
8.4 Parallel Port Registers (CR03) .................................................................................. 71
8.5 Hardware Monitor Registers (CR04) ......................................................................... 72
8.6 KBC Registers (CR05) .............................................................................................. 72
8.7 GPIO Registers (CR06) (All registers of GPIO are powered by VSB3V) .................. 73
8.8 VID Registers (CR07) ............................................................................................... 85
1.
2.
3.
4.
5.
6.
April, 2010
V0.19P
stm32/stm8
