F75113
F75113
Low Power GPIO with LED Function
Release Date: Dec, 2011
Version: V0.13P
Dec, 2011
V0.13P
F75113
F75113 Datasheet Revision History
Version
V0.10P
V0.11P
Date
2010/12
2011/01
4, 8
63-65
91-92
17, 21
30, 31
39, 40
48, 49
59, 60
74, 75
68
68
84
87
Page
Revision History
Preliminary version
1. Add SERIRQ on F75113U pin5
2. Add Register 50 ~ 54h
3. Update Reference Circuits
V0.12P
2011/07
V0.13P
2011/12
1. Update Global Control Register for LPC Interface
2. Update GPIO0X Input De-bounce Register
⎯
Index 16h
3. Update GPIO1X Input De-bounce Register
⎯
Index 26h
4. Update GPIO2X Input De-bounce Register
⎯
Index 36h
5. Update GPIO3X Input De-bounce Register
⎯
Index 46h
6. Update GPIO4X Input De-bounce Register
⎯
Index 76h
7. Add Chip ID1 & ID 2 Register
⎯
Index 5Ah, 5Bh
8. Add Vendor ID1 & ID2 Register
⎯
Index 5Dh, 5Eh
9. Delete 32 QFN Package
10.
Update Reference Circuits (for SPI)
1. Made Clarification and Correction
2. Modify Pin 9~16 Type
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies
mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales.
Dec, 2011
V0.13P
F75113
Table of Contents
1. GENERAL DESCRIPTION .......................................................................................................................................- 3 -
2. FEATURES ................................................................................................................................................................- 3 -
3. KEY SPECIFICATIONS ............................................................................................................................................- 4 -
4. BLOCK DIAGRAM ....................................................................................................................................................- 5 -
5. PIN CONFIGURATION..............................................................................................................................................- 6 -
6. PIN DESCRIPTION ...................................................................................................................................................- 7 -
6.1
6.2
6.3
Power Pin .................................................................................................................................................... - 7 -
GPIO Function ............................................................................................................................................. - 7 -
Access Interface .......................................................................................................................................... - 9 -
7. FUNCTIONAL DESCRIPTION ............................................................................................................................... - 10 -
A
CCESS
I
NTERFACE
................................................................................................................................................ - 10 -
GPIO F
UNCTION
.................................................................................................................................................... - 10 -
LED F
UNCTION
...................................................................................................................................................... - 13 -
SMI F
UNCTION
....................................................................................................................................................... - 13 -
W
ATCH
D
OG
T
IMER
F
UNCTION
................................................................................................................................. - 13 -
P
OWER
-D
OWN
C
ONTROL
F
UNCTION
........................................................................................................................ - 14 -
8. REGISTER DESCRIPTION .................................................................................................................................... - 16 -
Global Control Registers (for LPC interface)....................................................................................................... - 16 -
GPIO Control Registers ....................................................................................................................................... - 17 -
9. ELECTRICAL CHARACTERISTIC ........................................................................................................................ - 76 -
A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................ - 76 -
DC C
HARACTERISTICS
............................................................................................................................................ - 76 -
AC C
HARACTERISTICS
............................................................................................................................................ - 77 -
9.3.1 LPC INTERFACE ............................................................................................................................................. - 77 -
9.3.2
SERIALIZED IRQ INTERFACE.................................................................................................................... - 79 -
10. ORDERING INFORMATION ............................................................................................................................... - 82 -
11. TOP MARKING SPECIFICATION ....................................................................................................................... - 82 -
12. PACKAGE DIMENSIONS ................................................................................................................................... - 83 -
-1-
Dec,2011
V0.13P
F75113
13. APPLICATION CIRCUITS ................................................................................................................................... - 85 -
-2-
Dec,2011
V0.13P
F75113
1. General Description
F75113 is a low power general purpose IO chip providing 40 GPIO. Level or pulse mode can be
programmed by registers so all GPIO can be programmed to logic one, zero, high pulse or low pulse.
GPIO0X~GPIO2X can be programmed to be power LED. F75113 includes two sets of watchdog timer for
system reset. Besides, two power-down modes (Manual or Smart) can be selected to save power and
control the total consumption under 10uA, so F75113 can fit the requirement of mobile device such as PDA
or cell phone.
2. Features
Support up to 40 GPIO pins
Each GPIO pin can be programmed to be high/low level or pulse mode
Each GPIO pin has de-bounce function
Support 8 GPIO pins for low level(V
IH
> 0.9V, V
IL
<0.3V) input mode
24 pins can be programmed to be LED
8 pins has SMI function
Two sets of watchdog timer
Two power down mode selection --- Manual or Smart Power Management mode
Support LPC/SMBus/SPI interface
Package in 48-TQFP
-3-
Dec,2011
V0.13P
