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F81218

F81218D/DG

ISA/LPC to 6 UART Datasheet

Release Date: August, 2007

Version: V0.33P

F81218

August, 2007

V0.33P

F81218

F81218 Datasheet Revision History

Version

0.24P

0.25P

Date

2003/7/10

2003/07/31

Page

Revision History

Revised index 25h to index 26h

Updated WDT enable timer as power-on setting

24MHz clock input : 10 sec

48MHz clock input : 5 sec

0.26P

0.27P

0.28P

2003/09/16

2004/01/07

2005/04/15

0.29P

2006/03/24

Updated application circuit

Revised the pin naming, between Pin91 to Pin96

Added “Green Package” ordering information

Added Full Duplex Function for IR self test

(Bit 2 of IR control register index F1h)

Modified UART Clock Select Register (F0h) bit 1:0

description. Reserved 01/10/11 clock selection.

Added flow control registers of UART1~ UART6 register

F0h bit 4.

0.30P

0.31P

0.32P

0.33P

2006/04/03

2006/05/30

2007/7/5

2007/8/20

Added AC timing characteristics description.

Modified RS485 register description

Added note description of AC Timing characteristics.

Company readdress

Modify typo of pin type (Pin 85,86,87,88,89)

Please note that all data and specifications are subject to change without notice. All the trade marks of products and

companies mentioned in this data sheet belong to their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Customers using or selling these products for use

in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such

improper use or sales.

F81218

August, 2007

V0.33P

F81218

Table of Content

1. General Description ......................................................................................................................................... 1

2. Feature List ...................................................................................................................................................... 1

3. Pin Configuration............................................................................................................................................. 2

4. Pin Description................................................................................................................................................. 3

4.1 ISA/LPC Interface ................................................................................................................................. 3

4.2 UART Interface...................................................................................................................................... 5

4.3 GPIO pins............................................................................................................................................. 10

4.4 Power ................................................................................................................................................... 10

5. Functional Description................................................................................................................................... 11

5.1 LPC Interface .................................................................................................................................... 11

5.2 UART................................................................................................................................................ 11

5.3 IR Function ....................................................................................................................................... 16

5.4 Watch Dog Timer Function............................................................................................................... 17

5.5 Serial IRQ ......................................................................................................................................... 18

6. Register Description................................................................................................................................... 20

6.1 Global Control Register .................................................................................................................... 23

6.1.1 Software Reset Register – index 02h ........................................................................................ 23

6.1.2 Logic Device Select Register – index 07h................................................................................ 24

6.1.3 Device ID Register– index 20h, 21h......................................................................................... 24

6.1.4 Vendor ID Register– index 23h, 24h......................................................................................... 24

6.1.5 Clock Source Select Register – index 25h................................................................................ 24

6.1.6 GPIO Function Select Register ( ISA Interface Only ) – index 26h......................................... 25

6.1.7 Test Mode Register – index 2Fh ............................................................................................... 25

6.2 UART 1 Device Control Register (LDN 0) ......................................................................................... 26

6.2.1

Device Enable Register – index 30h.................................................................................. 26

6.2.2

I/O Port Select Register – index 60h.................................................................................. 26

6.2.3

I/O Port Select Register – index 61h.................................................................................. 26

6.2.4 IRQ Channel Select Register – index 70h ............................................................................. 26

6.2.5 UART 1 Clock Select Register – index F0h .......................................................................... 27

6.2.6 IR1 Control Register – index F1h.......................................................................................... 28

6.3 UART 2 Device Control Register (LDN 1) ......................................................................................... 28

6.3.1

Device Enable Register – index 30h.................................................................................. 28

6.3.2

I/O Port Select Register – index 60h.................................................................................. 28

6.3.3

I/O Port Select Register – index 61h.................................................................................. 29

6.3.4 IRQ Channel Select Register – index 70h ............................................................................. 29

F81218

August, 2007

V0.33P

F81218

6.3.5 UART 2 Clock Select Register – index F0h .......................................................................... 30

6.3.6 IR 2 Control Register – index F1h......................................................................................... 30

6.4 UART 3 Device Control Register (LDN 2) ......................................................................................... 31

6.4.1

Device Enable Register – index 30h.................................................................................. 31

6.4.2

I/O Port Select Register – index 60h.................................................................................. 31

6.4.3

I/O Port Select Register – index 61h.................................................................................. 31

6.4.4 IRQ Channel Select Register – index 70h ............................................................................. 31

6.4.5 UART 3 Clock Select Register – index F0h .......................................................................... 32

6.5 UART 4 Device Control Register (LDN 3) ......................................................................................... 32

6.5.1

Device Enable Register – index 30h.................................................................................. 32

6.5.2

I/O Port Select Register – index 60h.................................................................................. 33

6.5.3

I/O Port Select Register – index 61h.................................................................................. 33

6.5.4 IRQ Channel Select Register – index 70h ............................................................................. 33

6.5.5 UART 4 Clock Select Register – index F0h .......................................................................... 34

6.6 UART 5 Device Control Register (LDN 4) ......................................................................................... 34

6.6.1

Device Enable Register – index 30h.................................................................................. 34

6.6.2

I/O Port Select Register – index 60h.................................................................................. 34

6.6.3

I/O Port Select Register – index 61h.................................................................................. 35

6.6.5 IRQ Channel Select Register – index 70h ............................................................................. 35

6.6.6 UART 5 Clock Select Register – index F0h .......................................................................... 36

6.7 UART 6 Device Control Register (LDN 5) ......................................................................................... 36

6.7.1

Device Enable Register – index 30h.................................................................................. 36

6.7.2

I/O Port Select Register – index 60h.................................................................................. 36

6.7.3

I/O Port Select Register – index 61h.................................................................................. 36

6.7.4 IRQ Channel Select Register – index 70h ............................................................................. 37

6.7.5 UART 6 Clock Select Register – index F0h .......................................................................... 37

6.8 Address Decoder 0 Device Control Register (LDN 6) ........................................................................ 38

6.8.1

Device Enable Register – index 30h.................................................................................. 38

6.8.2

Address Decoder Select Register 0– index 60h................................................................. 38

6.8.3

Address Decoder Select Register 1– index 61h................................................................. 38

6.8.4

Address Mask Register – index 62h .................................................................................. 38

6.8.5

IRQIN0 Channel Select Register (Only for LPC) – index 70h ......................................... 39

6.9 Address Decoder 1 Device Control Register (LDN 7) ........................................................................ 39

6.9.1

Device Enable Register – index 30h.................................................................................. 39

6.9.2

Address Decoder Select Register 0 – index 60h................................................................ 39

6.9.3

Address Decoder Select Register 1 – index 61h................................................................ 40

6.9.4

Address Mask Register – index 62h .................................................................................. 40

F81218

August, 2007

V0.33P

F81218

6.9.5

IRQIN1 Channel Select Register (Only for LPC) – index 70h ......................................... 40

6.10 Watch Dog Timer Device Control Register (LDN 8) ........................................................................ 41

6.10.1

Device Enable Register – index 30h.................................................................................. 41

6.10.2

I/O Port Select Register – index 60h.................................................................................. 41

6.10.3

I/O Port Select Register – index 61h.................................................................................. 41

6.10.4 IRQ Channel Select Register – index 70h ......................................................................... 41

6.10.5

Timer Status and Control Register – index F0h................................................................. 42

6.10.6

Timer Count Number Register – index F1h....................................................................... 43

6.11 GPIO and PME Device Control Register (LDN 9)............................................................................ 43

6.11.1

GPIO Port 2 Control Register – index F0h........................................................................ 43

6.11.2

GPIO Port 1 Control Register – index F1h........................................................................ 43

6.11.3

GPIO Port 2 Output Data Control Register – index F2h ................................................... 44

6.11.4

GPIO Port 1 Output Data Register – index F3h ................................................................ 45

6.11.5

PME Event 1 Control Register – index F4h ...................................................................... 45

6.11.6

PME Event 2 Control Register – index F5h ...................................................................... 46

6.11.7

PME Event 3 Control Register – index F6h ...................................................................... 47

6.11.8

GPIO Port 2 Input Status Register – index F7h ................................................................. 47

6.11.9

GPIO Port 1 Input Status Register – index F8h ................................................................. 48

6.11.10 PME Real Time Status Register – index F9h..................................................................... 48

6.11.11 PME Edge Status 1 Register – index FAh ......................................................................... 48

6.11.12 PME Edge Status 2 Register – index FBh ......................................................................... 49

6.11.13 PME Edge Status 3 Register – index FCh ......................................................................... 49

7. Electron Characteristic................................................................................................................................ 51

7.1 Absolute Maximum Ratings ............................................................................................................. 51

7.2 DC Characteristics ............................................................................................................................ 51

7.3 AC Timing Characteristics................................................................................................................ 53

8. Ordering Information .................................................................................................................................. 54

9. Package Dimensions ................................................................................................................................... 55

10. Application Circuit....................................................................................................................................... 54

F81218

August, 2007

V0.33P