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Intel

LXT972M Single-Port 10/100 Mbps

PHY Transceiver

Datasheet

The Intel

LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast

Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It

provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access

Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported.

Operation mode can be set to auto-negotiation, parallel detection, or manual control. The device is

powered from a single 3.3V power supply.

Applications

■

Combination 10BASE-T/100BASE-TX

Network Interface Cards (NICs)

Wireless access points

Network printers

■

10/100 Personal Computer Memory Card

International Association (PCMCIA) cards

Cable Modems and Set-Top Boxes

Product Features

■

3.3V Operation

IEEE 802.3-compliant 10BASE-T or

100BASE-TX with integrated filters

Auto-negotiation and parallel detection

MII interface with extended register

capability

Robust baseline wander correction

■

Carrier Sense Multiple Access / Collision

Detection (CSMA/CD) or full-duplex

operation

JTAG boundary scan

MDIO serial port or hardware pin

configurable

Integrated, programmable LED drivers

48-pin Low-profile Quad Flat Package

RESET_L

ADDR[1:0]

MDIO

MDC

Management /

Mode Select

Logic

Power Supply

Clock

Generator

VCC

GND

REFCLK/XI

TX_EN

TXD[3:0]

TX PCS

Manchester

Encoder

Parallel/Serial

Converter

Scrambler

100

& Encoder

Auto

Negotiation

Set

OSP

Pulse

Shaper

Driver

TP Out

TPOP

TPON

TX_CLK

LED/CFG[3:1]

JTAG

COL

Collision

Detect

Clock

Generator

Media

Select

OSP

Adaptive EQ with

Baseline Wander

Cancellation

100TX

TDI

TDO

TMS

TCK

TRST_L

TP In

TPIP

TPIN

RX_CLK

RXD[3:0]

RX P CS

RX_DV

CRS

RX_ER

Serial-to-

Parallel

Carrier Sense Converter

Data Valid

Error Detect

100

Manchester

Decoder

Decoder &

Descrambler

OSP

Slicer

10BT

B3387-13

Document Number: 302875-005

Revision Date: 27-Oct-2005

Intel

LXT972M Single-Port 10/100 Mbps PHY Transceiver

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL

PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or

in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The Intel

LXT972M Single-Port 10/100 Mbps PHY Transceiver may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Intel

LXT972M Single-Port 10/100 Mbps PHY Transceiver

Contents

1.0

Introduction to This Document ......................................................................................... 10

1.1

1.2

2.0

3.0

4.0

5.0

Document Overview ............................................................................................10

Related Documents............................................................................................. 10

Block Diagram for Intel

LXT972M Transceiver............................................................... 11

Pin Assignments for Intel

LXT972M Transceiver ...........................................................12

Signal Descriptions for Intel

LXT972M Transceiver ....................................................... 15

Functional Description...................................................................................................... 21

5.1

Device Overview .................................................................................................22

5.1.1 Comprehensive Functionality ................................................................. 22

5.1.2 Optimal Signal Processing Architecture ................................................. 22

Network Media / Protocol Support.......................................................................23

5.2.1 10/100 Network Interface .......................................................................23

5.2.2 MII Data Interface ................................................................................... 25

5.2.3 Configuration Management Interface ..................................................... 25

Operating Requirements .....................................................................................28

5.3.1 Power Requirements ..............................................................................28

5.3.2 Clock Requirements ............................................................................... 28

Initialization.......................................................................................................... 29

5.4.1 MDIO Control Mode and Hardware Control Mode .................................31

5.4.2 Reduced-Power Modes .......................................................................... 31

5.4.3 Reset for Intel

LXT972M Transceiver................................................... 31

5.4.4 Hardware Configuration Settings ...........................................................33

Establishing Link .................................................................................................34

5.5.1 Auto-Negotiation.....................................................................................34

5.5.2 Parallel Detection ................................................................................... 35

MII Operation....................................................................................................... 36

5.6.1 MII Clocks............................................................................................... 37

5.6.2 Transmit Enable .....................................................................................38

5.6.3 Receive Data Valid ................................................................................. 38

5.6.4 Carrier Sense ......................................................................................... 39

5.6.5 Error Signals........................................................................................... 39

5.6.6 Collision .................................................................................................. 39

5.6.7 Loopback................................................................................................ 40

100 Mbps Operation ............................................................................................41

5.7.1 100BASE-X Network Operations ...........................................................41

5.7.2 Collision Indication ................................................................................. 44

5.7.3 100BASE-X Protocol Sublayer Operations ............................................ 45

10 Mbps Operation.............................................................................................. 50

5.8.1 10BASE-T Preamble Handling ............................................................... 50

5.8.2 10BASE-T Carrier Sense .......................................................................50

5.8.3 10BASE-T Dribble Bits ........................................................................... 50

5.8.4 10BASE-T Link Integrity Test ................................................................. 51

5.8.5 Link Failure ............................................................................................. 51

5.2

5.3

5.4

5.5

5.6

5.7

5.8

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Intel

LXT972M Single-Port 10/100 Mbps PHY Transceiver

5.9

5.10

5.8.6 10BASE-T SQE (Heartbeat) .................................................................. 51

5.8.7 10BASE-T Jabber .................................................................................. 51

5.8.8 10BASE-T Polarity Correction................................................................ 51

Monitoring Operations ......................................................................................... 52

5.9.1 Monitoring Auto-Negotiation................................................................... 52

5.9.2 Monitoring Next Page Exchange............................................................ 52

5.9.3 LED Functions........................................................................................ 53

5.9.4 LED Pulse Stretching ............................................................................. 54

Boundary Scan (JTAG 1149.1) Functions .......................................................... 55

5.10.1 Boundary Scan Interface........................................................................ 55

5.10.2 State Machine ........................................................................................ 55

5.10.3 Instruction Register ................................................................................ 55

5.10.4 Boundary Scan Register ........................................................................ 56

5.10.5 Device ID Register ................................................................................. 56

6.0

Application Information..................................................................................................... 57

6.1

6.2

Magnetics Information ......................................................................................... 57

Typical Twisted-Pair Interface ............................................................................. 57

7.0

Electrical Specifications ................................................................................................... 61

7.1

7.2

Electrical Parameters .......................................................................................... 61

Timing Diagrams ................................................................................................. 65

8.0

9.0

10.0

Intel

LXT972M Transceiver Package Specifications...................................................... 90

10.1

Top Label Markings............................................................................................. 91

11.0

Product Ordering Information ........................................................................................... 92

Figures

Intel

LXT972M Transceiver Block Diagram....................................................... 11

Pin Assignments for Intel

LXT972M Transceiver 48-Pin LQFP Package ......... 12

Management Interface Read Frame Structure ................................................... 27

Management Interface Write Frame Structure ................................................... 27

Initialization Sequence for Intel

LXT972M Transceiver ..................................... 30

Link Establishment Overview) ............................................................................. 34

Clocking for 10BASE-T ...................................................................................... 37

Clocking for 100BASE-X .................................................................................... 37

Clocking for Link Down Clock Transition ............................................................ 38

Intel

LXT972M Transceiver Loopback Paths .................................................... 40

100BASE-X Frame Format ................................................................................ 41

100BASE-TX Data Path ..................................................................................... 42

100BASE-TX Reception with No Errors ............................................................. 43

100BASE-TX Reception with Invalid Symbol ..................................................... 43

100BASE-TX Transmission with No Errors ........................................................ 44

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Intel

LXT972M Single-Port 10/100 Mbps PHY Transceiver

100BASE-TX Transmission with Collision .......................................................... 44

Intel

LXT972M Protocol Sublayers.................................................................... 45

LED Pulse Stretching ......................................................................................... 54

Intel

LXT972M Transceiver Typical Twisted-Pair Interface - Switch ................. 58

Intel

LXT972M Transceiver Typical Twisted-Pair Interface - NIC .....................59

Intel

LXT972M Transceiver Typical Media Independent Interface .................... 60

Intel

LXT972M Transceiver 100BASE-TX Receive Timing ............................... 65

Intel

LXT972M Transceiver 100BASE-TX Transmit Timing .............................. 66

Intel

LXT972M Transceiver 10BASE-T Receive Timing ................................... 67

Intel

LXT972M Transceiver 10BASE-T Transmit Timing .................................. 68

Intel

LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing ............... 69

Intel

LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing...................... 70

Intel

LXT972M Transceiver Auto-Negotiation and Fast Link Pulse Timing .......71

Intel

LXT972M Transceiver Fast Link Pulse Timing .......................................... 71

Intel

LXT972M Transceiver MDIO Input Timing ................................................ 72

Intel

LXT972M Transceiver MDIO Output Timing .............................................72

Intel

LXT972M Transceiver Power-Up Timing .................................................. 73

Intel

LXT972M Transceiver RESET_L Pulse Width and Recovery Timing .......74

PHY Identifier Bit Mapping ................................................................................. 78

Intel

LXT972M Transceiver LQFP Package Specifications............................... 90

Sample LQFP Package - Intel

LXT972M Transceiver ...................................... 91

Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel

LX972M Transceiver

Order Matrix for Intel

LXT972M Transceiver ..................................................... 92

Tables

Related Documents from Intel............................................................................. 10

Intel

LXT972M Transceiver Signal Types ......................................................... 13

Intel

LXT972M Transceiver LQFP Numeric Pin List.......................................... 13

Intel

LXT972M Transceiver MII Data Interface Signal Descriptions.................. 16

Intel

LXT972M Transceiver MII Controller Interface Signal Descriptions .......... 17

Intel

LXT972M Transceiver Network Interface Signal Descriptions .................. 17

Intel

LXT972M Transceiver Standard Bus and Interface Signal Descriptions... 17

Intel

LXT972M Transceiver Configuration and LED Driver Signal Descriptions 18

Intel

LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions . 19

Intel

LXT972M Transceiver JTAG Test Signal Descriptions ............................. 19

Intel

LXT972M Transceiver Pin Types and Modes ........................................... 20

Intel

LXT972M Transceiver - PHY Device Address Selections......................... 26

Hardware Configuration Settings for Intel

LXT972M Transceiver .....................33

Carrier Sense, Loopback, and Collision Conditions ............................................ 39

4B/5B Coding ...................................................................................................... 46

Valid JTAG Instructions....................................................................................... 55

BSR Mode of Operation ...................................................................................... 56

Device ID Register for Intel

LXT972M Transceiver ........................................... 56

Magnetics Requirements.....................................................................................57

I/O Pin Comparison of NIC and Switch RJ-45 Setups ........................................57

Absolute Maximum Ratings for Intel

LXT972M Transceiver ............................. 61

Recommended Operating Conditions for Intel

LXT972M Transceiver ..............61

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005