www.fairchildsemi.com
FAN53418
Synchronous DC-DC MOSFET Driver
Features
• Drives N-channel High-Side and Low-Side MOSFETs in
a synchronous buck configuration
• Internal Adaptive “Shoot-Through” Protection
• High Switching Frequency (> 500kHz)
– 30ns Output Rise/Fall Times w/3000pF load
– 20ns Propagation Delay
• 12V High-Side and 12V Low-Side Drive
• OD input for Output Disable – allows for synchronization
with PWM controller
• SOIC-8 Package
General Description
The FAN53418 is a high frequency, dual MOSFET driver
specifically designed to drive two power N-Channel
MOSFETs in a synchronous rectified buck converter.
These drivers combined with a FAN53168 Multi-Phase Buck
PWM controller and power MOSFETs form a complete core
voltage regulator solution for advanced microprocessors.
The FAN53418 drives both the upper and lower gates in a
synchronous rectifier to +12V. The upper gate drive imple-
ments bootstrapping with only an external capacitor and
diode required. This reduces implementation complexity
and allows the use of higher performance, cost effective,
N-Channel MOSFETs.
The output drivers in the FAN53418 have the capacity to
efficiently switch power MOSFETs at frequencies over
500kHz. Each driver is capable of driving a 3000pF load
with a ~20ns propagation delay and ~30ns transition time.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously. Addition-
ally an Output Disable function is included to synchronize
the driver with the PWM controller. The FAN53418 is
rated for operation from 0°C to +85°C and is available in a
low-cost SOIC-8 package.
Applications
• Multi-phase VRM/VRD regulators for Microprocessor
Power
• High Current/High Frequency DC/DC Converters
• High Power Modular Power Supplies
Basic Application
+12V
C BST
D1
Q1
1
BST
DRVH
8
L1
2
IN
FAN54318
3
OD
PGND
6
Q2
4
C VCC
VCC
DRVL 5
SW
7
C VIN
Figure 1. Basic Application Circuit
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FAN53418
Pin Configuration
BST
1
8
DRVH
IN
2
FAN53418
SOIC-8
7
SW
OD
3
6
PGND
VCC
4
5
DRVL
Pin Description
Pin Number
1
Pin Name
BST
Pin Function Description
Bootstrap Supply Input
. Provides voltage supply to high-side MOSFET driver.
Connect to bootstrap capacitor (typically 100nF to 1µF). See Applications
Section for detailed information.
PWM Signal Input
. This pin accepts a digital logic-level PWM switching signal
from the controller.
Output Disable
. When low, this pin disables PWM switching and pulls DRVH
and DRVL low.
Power Input
. +12V chip bias power. Bypass with a 1µF ceramic capacitor.
Low Side Gate Drive Output
. Connect to the gate of low-side power
MOSFET(s).
Power Ground
. Power ground connect close to low-side MOSFET to minimize
ground loops.
Switch Node Input
. Connect to switching node between HS and LS MOSFETs.
It is necessary for adaptive shoot-thru protection. Also it provides return for
high-side bootstrapped driver.
High Side Gate Drive Output
. Connect to the gate of high-side power
MOSFET(s).
2
3
4
5
6
7
IN
OD
VCC
DRVL
PGND
SW
8
DRVH
Internal Block Diagram
VCC
4
IN 2
1 BST
8 DRVH
Delay
+1V
7 SW
5 DRVL
+1V
OD 3
1kΩ
6 PGND
2
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FAN53418
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life
impaired. Functional operation under these conditions is not implied.
Parameter
Supply Voltage: V
CC
to PGND
SW to PGND
BST to SW Voltage: V
BST
– V
SW
BST Voltage: V
BST
– PGND
DRVH
DRVL (<200ns duration)
Voltage on any other pin
Min.
-0.3
-5
-0.3
-0.3
V
SW
– 0.3
-2
-0.3
Max.
+15
+15
+15
V
CC
+ 15
V
BST
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
Units
V
V
V
V
V
V
V
Thermal Information
Parameter
Operating Junction Temperature (T
J
)
Storage Temperature
Lead Soldering Temperature, 10 seconds
Vapor Phase, 60 seconds
Infrared, 15 seconds
Power Dissipation (P
D
) @ T
A
= 25°C
Thermal Resistance (
Θ
JA
)*
95
Min.
0
–65
Typ.
Max.
+150
+150
+300
+215
+220
1052
Units
°C
°C
°C
°C
°C
mW
°C/W
Recommended Operating Conditions
Parameter
Supply Voltage V
CC
Ambient Operating Temperature
Operating Junction Temperature (T
J
)
See Figure 1
Min.
10.8
0
0
Typ.
12
Max.
13.2
+85
+150
Units
V
°C
°C
Conditions
V
CC
to GND
Note:
1. Θ
JA
is defined as 2 oz., 4 layer copper PCB with 1 in
2
thermal pad.
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FAN53418
Electrical Specifications
(Vcc = 12V, and T
A
= 0°C to +85°C, V
BST
= 4V to 26V, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Input Supply
Supply Voltage Range
Supply Current
OD Input
Input High Voltage
Input Low Voltage
Input Current
Propagation Delay Time
2
PWM Input
Input High Voltage
Input Low Voltage
Input Current
High-Side Driver
Output Resistance,
Sourcing Current
Output Resistance,
Sinking Current
Transition Times
2
t
rDRVH
t
fDRVH
Propagation Delay
2,3
Low-Side Driver
Output Resistance,
Sourcing Current
Output Resistance,
Sinking Current
Transition Times
2
Propagation Delay
2,3
t
rDRVL
t
fDRVL
t
pdhDRVL
t
pdlDRVL
See Figure 3, C
LOAD
= 3nF
See Figure 3, C
LOAD
= 3nF
See Figure 3
See Figure 3
•
•
•
•
•
1.8
1.0
25
21
30
10
3.0
2.5
35
30
60
20
Ω
Ω
ns
ns
ns
ns
t
pdhDRVH
t
pdlDRVH
V
BST
– V
SW
= 12V
V
BST
– V
SW
= 12V
See Figure 3, V
BST
– V
SW
= 12V,
C
LOAD
=3nF
See Figure 3, V
BST
– V
SW
= 12V,
C
LOAD
=3nF
See Figure 3, V
BST
– V
SW
= 12V
See Figure 3, V
BST
– V
SW
= 12V
•
•
•
•
•
•
1.8
1.0
35
20
40
20
3.0
2.5
45
30
65
35
Ω
Ω
ns
ns
ns
ns
V
IH(PWM)
V
IL(PWM)
I
IL(PWM)
•
•
•
-1
3.5
0.8
+1
V
V
µA
V
IH(OD)
V
IL(OD)
I
IL(OD)
t
pdl(OD)
t
pdh(OD)
See Figure 2
See Figure 2
•
•
•
•
•
-1
15
20
2.8
0.8
+1
30
40
V
V
µA
ns
ns
V
CC
I
SYS
BST = 12V, IN = 0V
•
•
4.15
3
13.2
6
V
mA
Symbol
Conditions
Min.
Typ.
Max.
Units
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control.
2. AC Specifications guaranteed by design/characterization – NOT tested in production.
3. For propagation delays “t
pdh
” refers to low-to-high signal transition and “t
pdl
” refers to high-to-low signal transition.
4
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FAN53418
Timing Characteristics
VIH(OD)
OD
VIL(OD)
tpdl(OD)
90%
tpdh(OD)
HDRV/LDRV
10%
Figure 2. Output Disable Timing
IN
t f(DRVL)
t pdl(DRVL)
t pdl(DRVH)
t f(DRVH)
t r(DRVH)
t pdh(DRVH)
t r(DRVL)
DRVL
DRVH-SW
VTH
VTH
SW
1V
t pdh(DRVH)
Figure 3. Non-overlap Timing Diagram (Timing is referenced to the 90% and 10% points unless otherwise noted)
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