FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller
November 2013
FCM8531 — MCU Embedded and Configurable
3-Phase PMSM / BLDC Motor Controller
Features
Advanced Motor Controller (AMC)
Configurable Processing Core
-
Sensorless Field-Oriented Control (FOC) with
Speed Integral Method
-
Sensorless FOC with Sliding Mode
-
Hall Interface
Space Vector Modulation (SVM)
Sine-Wave & Square-Wave Generator
Programmable Current Leading Phase Control
Programmable Soft-Switching Control (Dead Time)
FCM8531RQY Certified by UL for IEC-60730-1
Class B Compliance with recognized marking:
Description
The FCM8531 is an application-specific parallel-core
processor for motor control that consists of an
Advanced Motor Controller (AMC) processor and a
®
MCS 51-compatible MCU processor. The AMC is the
core processor specifically designed for motor control. It
integrates a configurable processing core and peripheral
circuits to perform FOC and “Sensorless” motor control.
System control, user interface, communication interface,
and input/output interface can be programmed through
®
the embedded MCS 51 for different motor applications.
The advantage of FCM8531’s parallel-core processors
is that the two processors can work independently and
complement each other. The AMC processes the tasks
dedicated for motor controls, such as the motor control
algorithms, PWM controls, current sensing, real-time
over-current protection, and motor angle calculation.
The embedded MCU provides motor control commands
to the AMC to perform motor control activities through a
communication interface. This approach reduces the
software burden and simplifies the control system
program because complex motor control algorithms are
executed in the AMC. Fairchild provides the Motor
Control Development System (MCDS) IDE and MCDS
Programming Kit for users to develop software, compile
programs, and perform online debugging.
To meet IEC 60730-1 Class B safety standard for
household appliances, FCM8531 has FCM8531RQY
version in its family that has been certificated by UL for
the compliance. Users can directly utilize the UL
certificated AMC to quicken product development cycle
for electronic controlled PMSM/BLDC motor.
Embedded MCU
®
MCS 51 Compatible
63% of Instructions’ Execution Cycle <3 System
Clocks (3T)
Memory Size:
-
12 KB Flash Program Memory
-
256 +1 KB SRAM Data Memory
Extended16-Bit Multiplication / Division Unit (MDU)
≤17 General-Purpose Input / Output (GPIO) Pins
Full Duplex Serial Interface (UART)
2
I C Interface
Serial Peripheral Interface (SPI)
Three External Interrupts
Three 16-Bit Timers
Programmable 15-Bit Watchdog Timer (WDT)
Built-in Power-On Reset (POR)
Built-in Clock Generator
Two-Level Program Memory Lock
ADC and DAC
8-Channel, 10-Bit ADC
-
Auto-Trigger Sample & Hold
-
Four Trigger Mode Selections
-
Three Pre-AMP Gain Selections
1-Channel, 8-Bit DAC
Protections
Three Levels of Over-Current Protection (OCP)
Power Management
Idle Mode, Stop Mode, Sleep Mode
Development Supports
In System Programming (ISP)
On-Chip Debug Support (OCDS)
Applications
Sensorless IPM / SPM, BLDC / PMSM Motor
Fan, Blower, Pump, Compressor, etc.
Related Resources
AN-8202
—
FCM8531 User Manual - Hardware
Description
AN-8203
—
FCM8531 User Manual - Instruction Set
User Guide for FCM8531 Evaluation Board
© 2012 Fairchild Semiconductor Corporation
FCM8531 • Rev. 1.0.2
www.fairchildsemi.com
FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller
Ordering Information
Part Number
FCM8531QY
FCM8531RQY
Operating Temperature Range
-40 C to 85 C
-40 C to 85 C
o
o
o
o
Package
32-Lead, LQFP, JEDEC MS-026,
Variation BBA, 7 mm Square
32-Lead, LQFP, JEDEC MS-026,
Variation BBA, 7 mm Square
Packing Method
Tray
Tray
Application Diagram
5V
A
FCM8531
23 DVDD
VA 15
VSEN
DC-DC
Converter
5V
0.1µF
0.1µF
D
AVSS 17
22 AVDD
A
ISP Port
+5V
5V
A
24 V25
1µF
P02/U 27
P03/X 28
P04/V 29
P05/Y 30
25 DVSS
3.3
D
VPP
RST
SCL
SDA
GND
D
26 VPP
0.1µF
D
33
33
10K
D
3-Phase
Inverter
Motor
12 RST
1nF
10K
D
D
P06/W 31
P07/Z 32
33
1 P10
2 P11
3 P12
4 P13
5 P14
6 P15
7 P16
A
A
IA 21
IB 20
IC 19
40K 1%
40K 1%
40K 1%
<100p
A
R
S
A
5V
NTC
8 P17
5V
RUN/STOP
9
P24
CW/CCW
10 P25
D
VB 14
VC 13
OTP
5V
ADC0 18
SPEED
ADC3 16
A
FAULT
11 P26
A
Figure 1.
Typical Application Circuit
© 2012 Fairchild Semiconductor Corporation
FCM8531 • Rev. 1.0.2
www.fairchildsemi.com
2
FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller
Block Diagram
DVDD
23
V25
24
DVSS
25
D
VPP RST
26
12
AVSS AVDD
17
A
22
P02 / U
P03 / X
P04 / V
P05 / Y
P06 / W
P07 / Z
P10 / RX
P11 / TX
P12 / SCL
P13 / SDA
P14 / SPSSN
P15 / MOSI
P16 / MISO
P17 / SCK
P24 / CC0
P25 / CC1
P26 / CC2
27
28
29
30
31
32
1
2.5V
Power
Management
Unit
SLEEP
Clock
Generator
POR
AVDD
I
BIAS
21
Protection
Short
f
SYS
OC
Fault
IA
IB
IC
GPIO 0
20
AMC
UVWXYZ
PWM Engine
19
Monitor Bus
2
3
4
5
6
7
8
9
I/O Peripheral
Port
Angle Predictor
Flash PM
(12KB)
SRAM DM
(1K)
15
14
13
VA
VB
VC
GPIO 1
GPIO 2
Embedded MCU
ISP
WDT
UART
SPI
TIMER
IC
SFR
2
OCDS
MDU
MSFR
Configurable Processing
Core
MCS-51
Core
10-bit
ADC
8-bit
DAC
MUX
18
16
10
11
ADC0
ADC3 / AOUT
Figure 2.
Block Diagram
Marking Information
25
24
17
F ZXYTT
FCM8531
TPM
F-
Fairchild Logo
Z- Plant Code
X-1-Digit Year Code
Y- 1-Digit Week Code
TT: 2-Digit Die Run Code
T:Package Type (Q=LQFP)
P: Y=Green Package
M: Die Run Code
Figure 3.
FCM8531 Top Mark
32
1
8
9
16
F ZXYTT
FCM8531R
TPM
F-
Fairchild Logo
Z- Plant Code
X-1-Digit Year Code
Y- 1-Digit Week Code
TT: 2-Digit Die Run Code
R: UL60730 Certification
T:Package Type (Q=LQFP)
P: Y=Green Package
M: Die Run Code
Figure 4.
FCM8531R Top Mark
25
24
32
1
© 2012 Fairchild Semiconductor Corporation
FCM8531 • Rev. 1.0.2
8
9
16
17
www.fairchildsemi.com
3
Pin Configuration
V25
DVDD
AVDD
IA
IB
IC
ADC0
AVSS
FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller
DVSS
VPP
P02 / U
P03 / X
P04 / V
P05 / Y
P06 / W
P07 / Z
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
9
32
1 2 3 4 5 6 7 8
FCM8531
ADC3 / AOUT
VA
VB
VC
RST
P26 / CC2 / T2 / T0
P25 / CC1 / T1 / T2EX
P24 / CC0 / T0 / T2
Figure 5.
Pin Definitions
Pin #
Name
P10
1
RX
SCL
SPSSN
P11
2
TX
SDA
MOSI
P12
SCL
3
RX
MISO
ISP_SCL
P13
SDA
4
TX
SCK
ISP_SDA
P14
SPSSN
5
RX
SCL
TDO
Type
I/O
I
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I
I/O
I
I/O
I/O
O
I/O
I/O
I/O
I/O
I
I/O
O
Data Receive (UART)
Serial Clock (I C)
SPI Slave Select (SPI)
2
P10 / RX / SCL / SPSSN
P11 / TX / SDA / MOSI
P12 / SCL / RX / MISO / ISP_SCL
P13 / SDA / TX / SCK / ISP_SDA
P14 / SPSSN / TDO / RX / SCL
P15 / MOSI / TDI / TX / SDA
P16 / MISO / TMS / SCL / RX
P17 / SCK / TCK / SDA / TX
Pin Configuration
Description
Bit 0 of Port 1.
General-purpose input/output pin with internal pull-up resistor.
Bit 1 of Port 1.
General-purpose input/output pin with internal pull-up resistor.
Serial Data Transmit (UART)
Serial Data (I C)
Master Data Output and Slave Data Input (SPI)
Bit 2 of Port 1.
General-purpose input/output pin with internal pull-up resistor.
Serial Clock (I C)
Data Receive (UART)
Master Data Input and Slave Data Output (SPI)
ISP Serial Clock.
Serial clock input in ISP Mode.
Bit 3 of Port 1.
General-purpose input/output pin with internal pull-up resistor.
Serial Data (I C)
Serial Data Transmit (UART)
Serial Clock (SPI)
ISP Serial Data.
Serial data input/output pin in ISP Mode.
Bit 4 of Port 1.
General-purpose input/output pin with internal pull-up resistor.
SPI Slave Select (SPI)
Data Receive (UART)
Serial Clock (I C)
Test Data Output.
Test data output in OCDS Mode.
Continued on the following page…
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© 2012 Fairchild Semiconductor Corporation
FCM8531 • Rev. 1.0.2
www.fairchildsemi.com
4
FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller
Pin Definitions
(Continued)
Pin #
Name
P15
MOSI
6
TX
SDA
TDI
P16
MISO
7
SCL
RX
TMS
P17
SCK
8
SDA
TX
TCK
P24
9
CC0
T0
T2
P25
10
CC1
T1
T2EX
P26
11
CC2
T2
T0
12
13
14
15
RST
VC
VB
VA
ADC3
AOUT
17
18
19
AVSS
ADC0
IC
Type
I/O
I/O
O
I/O
I
I/O
I/O
I/O
I
I
I/O
I/O
I/O
O
I
I/O
I/O
I
I
I/O
I/O
I
I
I/O
I/O
I
I
I
AI
AI
AI
AI
AO
P
AI
AI
Description
Bit 5 of Port 1.
General-purpose input/output pin with internal pull-up resistor.
Master Data Output and Slave Data Input (SPI)
Serial Data Transmit (UART)
Serial Data (I C)
Test Data Input.
Test data input in OCDS Mode.
Bit 6 of Port 1.
General-purpose input/output pin with internal pull-up resistor.
Master Data Input and Slave Data Output (SPI)
Serial Clock (I C)
Data Receive (UART)
Test Mode Select.
Test mode select in OCDS Mode.
Bit 7 of Port 1.
General-purpose input/output pin with internal pull-up resistor.
Serial Clock (SPI)
Serial Data (I C)
Serial Data Transmit (UART)
Test Clock.
Test clock input in OCDS Mode.
Bit 4 of Port 2.
General-purpose input/output pin with internal pull-up resistor.
TIMER2 Compare/Capture Channel 0
TIMER0 External Input
TIMER2 External Input
Bit 5 of Port 2.
General-purpose input/output pin with internal pull-up resistor.
TIMER2 Compare/Capture Channel 1
TIMER1 External Input
TIMER2 External Trigger
Bit 6 of Port 2.
General-purpose input/output pin with internal pull-up resistor.
TIMER2 Compare/Capture Channel 2
TIMER2 External Input
TIMER0 External Input
System Reset.
Hardware reset input, active HIGH.
Analog Input.
10-bit ADC input (middle sampling rate). The ADC result stores in VCL and
VCH registers (2Ch, 2Dh) of MSFR.
Analog Input.
10-bit ADC input (middle sampling rate). The ADC result stores in VBL and
VBH registers (2Ah, 2Bh) of MSFR.
Analog Input.
10-bit ADC input (middle sampling rate). The ADC result stores in VAL and
VAH registers (28h, 29h) of MSFR.
Analog Input.
10-bit ADC input (low sampling rate).The ADC result stores in ADC3L and
ADC3H registers (36h, 37h) of MSFR.
Analog Output.
8-bit DAC output set by DAC3 register (47h) of MSFR.
Analog Ground
Analog Input.
10-bit ADC input (low sampling rate). The ADC result stores in ADC0L and
ADC0H registers (30h, 31h) of MSFR.
Phase C Current Input.
10-bit ADC input (high sampling rate). The ADC result stores in
ICL and ICH registers (24h, 25h) of MSFR.
Continued on the following page…
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© 2012 Fairchild Semiconductor Corporation
FCM8531 • Rev. 1.0.2
www.fairchildsemi.com
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