FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
FDMF6707B - Extra-Small, High-Performance, High-
Frequency DrMOS Module
Benefits
Ultra-Compact 6x6mm PQFN, 72% Space-Saving
Compared to Conventional Discrete Solutions
Fully Optimized System Efficiency
Clean Sw itching Waveforms w ith Minimal Ringing
High-Current Handling
Description
The XS™ DrMOS family is ON Semiconductor’s next-
generation, fully optimized, ultra-compact, integrated
MOSFET plus driver pow er stage solution for high-
current, high-frequency, synchronous buck DC-DC
applications. The FDMF6707B integrates a driver IC, tw o
pow er MOSFETs, and a bootstrap Schottky diode into a
thermally enhanced, ultra-compact 6x6 mm PQFN
package.
With an integrated approach, the complete sw itching
pow er stage is optimized for driver and MOSFET
dynamic performance, system inductance, and pow er
XS™
Dr MOS
uses
ON
MOSFET
R
DS(ON)
.
Semiconductor's
high-performance
Pow erTrench®
MOSFET technology, w hich dramatically reduces sw itch
ringing, eliminating the snubber circuit in most buck
converter applications.
A new driver IC w ith reduced dead times and
propagation delays further enhances performance. A
ther mal w arning function w arns of potential over-
temperature situations. FDMF6707B also incorporates
features such as Skip Mode (SMOD) for improved light-
load efficiency, along w ith a 3-state 3.3 V PWM input for
compatibility w ith a w ide range of PWM controllers.
Features
Over 93% Peak-Efficiency
High-Current Handling of 50 A
High-Performance PQFN Copper-Clip Package
3-State 3.3 V PWM Input Driver
Skip-Mode SMOD# (Low -Side Gate Turn Off) Input
Thermal Warning Flag for Over-Temperature
Condition
Driver Output Disable Function (DISB# Pin)
Internal Pull-Up and Pull-Dow n for SMOD# and
DISB# Inputs, Respectively
ON Semiconductor Pow erTrench® Technology
MOSFETs for Clean Voltage Waveforms and
Reduced Ringing
ON Semiconductor SyncFET™ (Integrated
Schottky Diode) Technology in the Low -Side
MOSFET
Integrated Bootstrap Schottky Diode
Adaptive Gate Drive Timing for Shoot-through
Protection
Under-Voltage Lockout (UVLO)
Optimized for Sw itching Frequencies up to 1 MHz
Low -Profile SMD Package
ON Semiconductor Green Packaging and RoHS
Compliant
Based on the Intel® 4.0 DrMOS Standard
Applications
High-Performance Gaming Motherboards
Compact Blade Servers, V-Core and Non-V-Core
DC-DC Converters
Desktop Computers, V-Core and Non-V-Core
DC-DC Converters
Workstations
High-Current DC-DC Point-of-Load (POL)
Converters
Netw orking and Telecom Microprocessor Voltage
Regulators
Small Form-Factor Voltage Regulator Modules
Ordering Information
Part Number
FDMF6707B
Current Rating
50 A
Package
40-Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package
Top Mark
FDMF6707B
© 2011 Semiconductor Components Industries, LLC.
December-2017, Rev. 2
Publication Order Number:
FDMF6707B/D
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Typical Application Circuit
V
5V
R
VCIN
C
VDRV
C
VCIN
C
VIN
V
IN
3V ~ 15V
VDRV
VCIN
VIN
DISB
PWM
Input
OFF
ON
DISB#
BOOT
PWM
R
BOOT
C
BOOT
PHASE
FDMF6707B
SMOD#
VSWH
THWN#
CGND
PGND
Open-
Drain
Output
L
OUT
V
OUT
C
OUT
Figure 1.
Typical Application Circuit
DrMOS Block Diagram
VDRV
VCIN
UVLO
BOOT
VIN
Q1
HS Power
MOSFET
D
Boot
GH
Lev el Shift
30kΩ
DISB#
10µA
V
CIN
R
UP_PWM
PWM
R
DN_PWM
Input
3-State
Logic
GH
Logic
PHASE
Dead-Time
Control
V
DRV
GL
Logic
VSWH
GL
30kΩ
THWN#
Temp.
Sense
V
CIN
Q2
LS Power
MOSFET
10µA
CGND
SMOD#
PGND
Figure 2.
DrMOS Block Diagram
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2
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Pin Configuration
SMOD#
PHASE
SMOD#
PHASE
CGND
BOOT
VDRV
CGND
BOOT
VDRV
VCIN
VCIN
VIN
VIN
GH
NC
VIN
VIN
GH
NC
1
2
3
4
5
6
7
8
9
10
10
9
8
7
6
5
4
3
2
1
PWM
DISB#
THWN
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
11
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
40
39
38
37
36
35
34
33
32
31
11
PWM
DISB#
THWN
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
12
13
15
14
16
17
18
19
20
VSWH
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
Pin Definitions
Pin #
1
2
3
4
5, 37, 41
6
7
8
9 - 14, 42
15, 29 -
35, 43
16 – 28
36
38
Name
When SMOD#=HIGH, the low -side driver is the inverse of PWM input. When SMOD#=LOW,
SMOD# the low -side driver is disabled. This pin has a 10 µA internal pull-up current source. Do not add
a noise filter capacitor.
VCIN
VDRV
BOOT
CGND
GH
IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND.
Pow er for gate driver. Minimum 1 µF ceramic capacitor is recommended connected as close as
possible from this pin to CGND.
Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a
bootstrap capacitor from this pin to PHASE.
IC ground. Ground return for driver IC.
For manufacturing test only. This pin must float. It must not be connected to any pin.
PHASE Sw itch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.
NC
VIN
VSWH
PGND
GL
THWN#
No connect. The pin is not electrically connected internally, but can be connected to VIN for
convenience.
Pow er input. Output stage supply voltage.
Sw itch node input. Provides return for high-side bootstrapped driver and acts as a sense point
for the adaptive shoot-through protection.
Pow er ground. Output stage ground. Source pin of the low -side MOSFET.
For manufacturing test only. This pin must float. It must not be connected to any pin.
Thermal w arning flag, open collector output. When temperature exceeds the trip limit, the
output is pulled LOW. THWN# does not disable the module.
Output disable. When LOW, this pin disables the pow er MOSFET sw itching (GH and GL are
held LOW). This pin has a 10 µA internal pull-dow n current source. Do not add a noise filter
capacitor.
PWM signal input. This pin accepts a 3-state 3.3 V PWM signal from the controller.
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3
40
39
38
37
36
35
34
33
32
31
12
CGND
41
VIN
42
VIN
42
CGND
41
13
14
15
16
17
VSWH
43
VSWH
43
18
19
20
30
29
28
27
26
25
24
23
22
21
21
PGND
22
PGND
23
PGND
24
PGND
25
PGND
26
PGND
27
PGND
28
PGND
29
VSWH
30
VSWH
Figure 3.
Bottom View
Figure 4.
Top View
Description
39
40
DISB#
PWM
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VIN to PGND, CGND Pins
Parameter
VCIN, VDRV, DISB#, PWM, SMOD#, GL, THWN# to CGND Pins
BOOT, GH to VSWH, PHASE Pins
BOOT, PHASE, GH to CGND Pins
VSWH to CGND/PGND (DC Only)
VSWH to PGND (< 20 ns)
BOOT to VDRV
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-8.0
-0.1
Max.
6.0
25.0
6.0
25.0
25.0
25.0
22.0
7.0
50
45
3.5
Unit
V
I
THWN#
(
THWN# Sink Current
f
SW
=300 kHz
f
SW
=1 MHz
mA
I
O(AV)
Error!
Reference
V
IN
=12V, V
O
=1.0V
source not
)
found.
θ
JPCB
T
A
T
J
T
STG
ESD
Junction-to-PCB Thermal Resistance
Ambient Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Electrostatic Discharge Protection
A
°C/W
°C
°C
°C
V
-40
-55
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
2000
1000
+125
+150
+150
Note:
1. I
O(AV)
is rated using ON Semiconductor’s DrMOS evaluation board, at T
A
= 25°C, w ith natural convection cooling.
This rating is limited by the peak DrMOS temperature, T
J
= 150°C, and varies depending on operating conditions
and PCB layout. This rating can be changed w ith different application settings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet spec ifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CIN
V
DRV
V
IN
Parameter
Control Circuit Supply Voltage
Gate Drive Circuit Supply Voltage
Output Stage Supply Voltage
(2)
Min.
4.5
4.5
3.0
Typ.
5.0
5.0
12.0
Max.
5.5
5.5
15.0
Unit
V
V
V
Note:
2. Operating at high V
IN
can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes
during MOSFET sw itching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must
remain at or below the Absolute Maximum Ratings show n in the table above.
Refer to the “Application
Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.
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4
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Electrical Characteristics
Typical values are V
IN
= 12 V, V
CIN
= 5 V, V
DRV
= 5 V, and T
A
= +25°C unless otherw ise noted.
Symbol
Basic Operation
I
Q
UVLO
UVLO
_Hyst
R
UP_PWM
R
DN_PWM
V
IH_PWM
V
TRI_HI
V
TRI_LO
V
IL_PWM
V
HiZ_PWM
R
UP_PWM
R
DN_PWM
V
IH_PWM
V
TRI_HI
V
TRI_LO
V
IL_PWM
V
HiZ_PWM
DISB# Input
V
IH_DISB
V
IL_DISB
I
PLD
t
PD_DISBL
t
PD_DISBH
Parameter
Quiescent Current
UVLO Threshold
UVLO Hysteresis
Pull-Up Impedance
Pull-Dow n Impedance
PWM High Level Voltage
3-State Upper Threshold
3-State Low er Threshold
PWM Low Level Voltage
Condition
I
Q
=I
VCIN
+I
VDRV
, PWM=LOW or HIGH or Float
V
CIN
Rising
Min. Typ. Max. Unit
2
2.9
3.1
0.4
26
12
1.88
1.84
0.70
0.62
1.40
2.25
2.20
0.95
0.85
160
1.60
26
12
2.00
1.94
0.75
0.66
1.45
2.25
2.20
0.95
0.85
160
1.60
2.50
2.46
1.15
1.09
200
1.80
2.61
2.56
1.19
1.13
200
1.90
3.3
mA
V
V
kΩ
kΩ
V
V
V
V
ns
V
kΩ
kΩ
V
V
V
V
ns
V
PWM Input
(VCIN = VDRV = 5 V +/- 10%)
t
D_HOLD-OFF
3-State Shutoff Time
3-State Open Voltage
Pull-Up Impedance
Pull-Dow n Impedance
PWM High Level Voltage
3-State Upper Threshold
3-State Low er Threshold
PWM Low Level Voltage
3-State Open Voltage
PWM Input
(VCIN = VDRV = 5 V ±5%)
t
D_HOLD-OFF
3-State Shutoff Time
High-Level Input Voltage
Low -Level Input Voltage
Pull-Dow n Current
Propagation Delay
Propagation Delay
PWM=GND, Delay Betw een DISB# from
HIGH to LOW to GL from HIGH to LOW
PWM=GND, Delay Betw een DISB# from
LOW to HIGH to GL from LOW to HIGH
2
0.8
10
25
25
V
V
µA
ns
ns
SMOD# Input
V
IH_SMOD
V
IL_SMOD
I
PLU
t
PD_SLGLL
t
PD_SHGLH
High-Level Input Voltage
Low -Level Input Voltage
Pull-Up Current
Propagation Delay
Propagation Delay
PWM=GND, Delay Betw een SMOD# from
HIGH to LOW to GL from HIGH to LOW
PWM=GND, Delay Betw een SMOD# from
LOW to HIGH to GL from LOW to HIGH
10
10
10
2
0.8
V
V
µA
ns
Ns
Continued on the following page…
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