FIN1031 3.3V LVDS 4-Bit High Speed Differential Driver
July 2001
Revised July 2001
FIN1031
3.3V LVDS 4-Bit High Speed Differential Driver
General Description
This quad driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The driver translates LVTTL signal levels to LVDS lev-
els with a typical differential output swing of 350mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed trans-
fer of clock and data.
The FIN1031 can be paired with its companion receiver,
the FIN1032, or any other Fairchild LVDS receiver.
Features
s
Greater than 400Mbs data rate
s
3.3V power supply operation
s
0.4ns maximum differential pulse skew
s
2.0ns maximum propagation delay
s
Low power dissipation
s
Power OFF protection
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
Pin compatible with equivalent RS-422 and LVPECL
devices
s
16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
FIN1031M
FIN1031MTC
Package Number
M16A
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Inputs
EN
H
H
H
X
X
X
L
H
=
HIGH Logic Level
X
=
Don’t Care
Connection Diagram
Outputs
D
IN
H
L
OPEN
H
L
OPEN
X
D
OUT+
H
L
L
H
L
L
Z
D
OUT−
L
H
H
L
H
H
Z
EN
X
X
X
L
L
L
H
L
=
LOW Logic Level
Z
=
High Impedance
Pin Descriptions
Pin Name
D
IN1
, D
IN2
, D
IN3
, D
IN4
Description
LVTTL Data Inputs
D
OUT1+
, D
OUT2+
, D
OUT3+
, D
OUT4+
Non-Inverting Driver Outputs
D
OUT1−
, D
OUT2−
, D
OUT3−
, D
OUT4−
Inverting Driver Outputs
EN
EN
V
CC
GND
Driver Enable Pin
Inverting Driver Enable Pin
Power Supply
Ground
© 2001 Fairchild Semiconductor Corporation
DS500507
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FIN1031
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
@V
CC
≥
3V
@V
CC
=
0V
DC Output Voltage (V
OUT
)
@V
CC
=
0V
Driver Short Circuit Current (I
OSD
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
260
°
C
−
0.5V to
+
4.6V
−
0.5V to
+
6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
Continuous
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Operating Temperature (T
A
)
3.0V to 3.6V
0 to V
CC
−
40
°
C to
+
85
°
C
−
65
°
C to
+
150
°
C
150
°
C
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
≥
8000V
≥
600V
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
I
OFF
I
OS
V
IH
V
IL
I
IN
I
OZ
I
I(OFF)
V
IK
I
CC
Parameter
Output Differential Voltage
V
OD
Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
Power Off Output Current
Short Circuit Output Current
Input HIGH Voltage
Input LOW Voltage
Input Current
Disabled Output Leakage Current
Power-OFF Input Current
Input Clamp Voltage
Power Supply Current
V
IN
=
0V or V
CC
EN
=
0.8V, EN
=
2.0V
V
OUT
=
0V or 4.7V
V
CC
=
0V, V
IN
=
0V or 3.6V
I
IK
= −18
mA
No Load, V
IN
=
0V or V
CC
, Driver Enabled
R
L
=
100
Ω,
Driver Disabled
R
L
=
100
Ω,
V
IN
=
0V or V
CC
, Driver Enabled
C
IN
C
OUT
Input Capacitance
Output Capacitance
−1.5
3.2
3.2
17.9
7
4
5
5
25
pF
pF
mA
V
CC
=
0V, V
OUT
=
0V or 3.6V
V
OUT
=
0V, Driver Enabled
V
OD
=
0V, Driver Enabled
2.0
GND
R
L
=
100Ω, Driver Enabled,
See Figure 1
1.125
1.25
Test Conditions
Min
250
Typ
(Note 2)
350
450
25
1.375
25
±20
−6
±6
V
CC
0.8
±20
±20
±20
Max
Units
mV
mV
V
mV
µA
mA
V
V
µA
µA
µA
V
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
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2
FIN1031
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLHD
t
PHLD
t
TLHD
t
THLD
t
SK(P)
t
SK(LH)
t
SK(HL)
t
SK(PP)
f
MAX
t
ZHD
t
ZLD
t
HZD
t
LZD
Parameter
Differential Propagation Delay
LOW-to-HIGH
Differential Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)
Differential Output Enable Time from Z to HIGH
Differential Output Enable Time from Z to LOW R
L
=
100Ω, C
L
=
10 pF,
Differential Output Disable Time from HIGH to Z See Figure 4 and Figure 5 (Note 7)
Differential Output Disable Time from LOW to Z
200
275
2.5
2.7
3.2
3.4
5.0
5.0
5.0
5.0
R
L
=
100
Ω,
C
L
=
10 pF,
See Figure 2 and Figure 3 (Note 7)
Test Conditions
Min
Typ
(Note 3)
0.8
0.8
0.6
0.6
1.4
1.4
0.85
0.85
2.0
2.0
1.2
1.2
0.4
0.3
1.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
f
MAX
Criteria: Input t
R
=
t
F
<
1 ns, 0V to 3V, 50% Duty Cycle; Output V
OD
>
250 mV, 45% to 55% Duty Cycle; all output channels switching in phase.
Note 7:
Test Circuits in Figure 2 and Figure 4 are simplified representations of test fixture and DUT loading.
3
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FIN1031
Note A:
All input pulses have frequency
=
10 MHz, t
R
or t
F
=
1 ns
Note B:
C
L
includes all fixture and instrumentation capacitances
FIGURE 1. Differential Driver DC Test Circuit
FIGURE 2. Differential Driver Propagation Delay and
Transition Time Test Circuit
Note B:
All input pulses have the frequency
=
10 MHz, t
R
or t
F
=
1 ns
Note A:
C
L
includes all fixture and instrumentation capacitances
FIGURE 3. AC Waveforms
FIGURE 4. Differential Driver Enable and
Disable Test Circuit
FIGURE 5. Enable and Disable AC Waveforms
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4
FIN1031
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
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