FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Connection Diagrams
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NC
A1
A2
VSS
1
2
8
7
VCC
NC
SCL
SDA
24C04
3
4
6
5
See Package Number N08E, M08A and MTC08
Pin Names
A1,A2
V
SS
SDA
SCL
NC
V
CC
Device Address Inputs
Ground
Serial Data I/O
Serial Clock Input
No Connection
Power Supply
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NC
A1
A2
VSS
1
2
8
7
VCC
WP
SCL
SDA
24C05
3
4
6
5
See Package Number N08E, M08A and MTC08
Pin Names
A1,A2
V
SS
SDA
SCL
WP
V
CC
NC
Device Address Inputs
Ground
Serial Data I/O
Serial Clock input
Write Protect
Power Supply
No Connection
2
FM24C04U/05U Rev. A.3
www.fairchildsemi.com
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Ordering Information
FM
24
C
XX
U
F
LZ
E
XXX
Package
Letter
N
M8
MT8
Blank
V
E
Blank
L
LZ
Description
8-pin DIP
8-pin SOIC
8-pin TSSOP
0 to 70°C
-40 to +125°C
-40 to +85°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
100KHz
400KHz
Ultralite CS100UL
4K
4K with Write Protect
CMOS Technology
IIC
Fairchild Non-Volatile
Memory
Temp. Range
Voltage Operating Range
SCL Clock Frequency
Blank
F
U
04
05
C
Process
Density
Interface
24
FM
3
FM24C04U/05U Rev. A.3
www.fairchildsemi.com
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Product Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 seconds)
ESD Rating
–65°C to +150°C
–0.3V to 6.5V
+300°C
2000V min.
Operating Conditions
Ambient Operating Temperature
FM24C04U/05U
FM24C04UE/05UE
FM24C04UV/05UV
Positive Power Supply
FM24C04U/05U
FM24C04UL/05UL
FM24C04ULZ/05ULZ
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
DC Electrical Characteristics (2.7V to 5.5V)
Symbol
Parameter
Test Conditions
Min
I
CCA
I
SB
(Note 3)
I
LI
I
LO
V
IL
V
IH
V
OL
Active Power Supply Current
Standby Current
f
SCL
= 400 KHz ("F" version)
f
SCL
= 100 KHz
V
IN
= GND
or V
CC
V
CC
= 2.7V - 5.5V
V
CC
= 2.7V - 5.5V (L)
V
CC
= 2.7V - 4.5V (LZ)
Limits
Typ
(Note 1)
0.2
10
1
0.1
0.1
0.1
Units
Max
1.0
50
10
1
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
mA
µA
µA
µA
µA
µA
V
V
V
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
–0.3
V
CC
x 0.7
I
OL
= 3 mA
Capacitance
T
A
= +25°C, f = 100/400 KHz, V
CC
= 5V
(Note 2)
Symbol
C
I/O
C
IN
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
Conditions
V
I/O
= 0V
V
IN
= 0V
Max
8
6
Units
pF
pF
Note 1:
Typical values are T
A
= 25°C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.
Note 2:
This parameter is periodically sampled and not 100% tested.
Note 3:
The "L" and "LZ" versions can be operated in the 2.7V to 5.5V V
CC
range. However, for a standby current (I
SB
) of 1µA, the V
CC
should be within 2.7V to 4.5V.
4
FM24C04U/05U Rev. A.3
www.fairchildsemi.com
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input & Output Timing Levels
Output Load
V
CC
x 0.1 to V
CC
x 0.9
10 ns
V
CC
x 0.3 to V
CC
x 0.7
1 TTL Gate and C
L
= 100 pF
AC Testing Input/Output Waveforms
0.9V
CC
0.1V
CC
0.7V
CC
0.3V
CC
Read and Write Cycle Limits (Standard and Low V
CC
Range 2.7V - 5.5V)
Symbol
f
SCL
T
I
Parameter
SCL Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
IN
Pulse width)
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
4.5V to 5.5V V
CC
2.7V to 4.5V V
CC
100 KHz
Min
Max
100
100
0.3
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
300
10
15
3.5
400 KHz
Min
Max
400
50
0.1
1.3
0.6
1.5
0.6
0.6
0
100
0.3
300
0.6
50
10
15
0.9
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
WR
(Note 4)
Note 4:
The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C04U/05U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
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FPGA/CPLD
