FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261
FlexQ II
TM
3.3 Volt Synchronous x9 First-In/First-Out Queue
Memory Configuration
524,288 x 9
262,144 x 9
131,072 x 9
65,536 x 9
32,768 x 9
16,384 x 9
Part Number
FQV2111
FQV2101
FQV291
FQV281
FQV271
FQV261
Key Features
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Industry leading First-In/First-Out Queues (up to 133MHz)
Write cycle time of 7.5ns independent of Read cycle time
Read cycle time of 7.5ns independent of Write cycle time
User selectable input and output port bus-sizing
Big Endian/Little Endian user selectable byte representation
3.3V power supply
5V input tolerant on all control and data input pins
5V output tolerant on all flags and data output pins
Master Reset clears all previously programmed configurations including Write and Read pointers.
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations.
First Word Fall Through (FWFT) and Standard Timing modes
Preset for Almost Full ( PRAF ) and Almost Empty ( PRAE ) offsets values
Parallel/Serial programming of PRAF and PRAE offset values
Full, Empty, Almost Full, Almost Empty and Half Full indicators
Asynchronous output enable tri-state data output drivers
Data retransmission
Available package: 64 - pin Plastic Thin Quad Flat Pack (TQFP), 64 – pin Slim Thin Quad Flat Pack (STQFP)
(0°C to 70°C) Commercial operating temperature available for cycle time of 7.5ns and above
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
HBA’s FlexQ™ II offers industry leading FIFO queuing bandwidth (up to 1.5 Gbps) with a wide range of memory
configurations (from 16,384 x 9 to
524,288
x 9). System designer has full flexibility of implementing deeper and wider queues
using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between
transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation
of virtual queue depths.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching
capability.
Master Reset clears all previously programmed configurations by providing a low pulse on
MRST
pin. In addition, Write and
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will
initialize Write and Read pointers to zero.
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high
transition of RCLK. Subsequent reads from the queue will require asserting
REN
. This feature is useful when implementing
depth expansion functions. In this mode,
DRDY
and QRDY are used instead of
FULL
and
EMPTY
respectively.
In Standard mode, always assert
REN
for read operation.
FULL
and
EMPTY
are used instead of
DRDY
and QRDY
respectively.
3F209C
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2002
Page 1 of 1
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261
FlexQ II
Product Description (Continued)
PRAF
,
PRAE
, and
HALF
are available in either FWFT or Standard mode.
PRAF
and
PRAE
can operate in either
synchronous or asynchronous modes.
TM
At any time, data previously read from the queue can be retransmitted by asserting
RET
pin at the low to high transition of RCLK
for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical
0
th
(Read pointer = zero), location of the queue.
These FlexQ™ II devices have low power consumption, hence minimizing system power requirements. In addition, industry
standard 64 - pin Plastic TQFP and 64 - pin STQFP are offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
Block Diagram of Single Synchronous Queue
524,288 x 9 / 262,144 x 9 / 131,072 x 9 / 65,536 x 9 / 32,768 x 9 / 16,384 x 9
PARTIAL RESET (PRST )
MASTER RESET (MRST)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD ( LOAD)
DATA IN (D
8 - 0
)
SERIAL DATA ENABLE (SDEN)
FIRST WORD FALL THROUGH/
SERIAL DATA INPUT (FWFT/SDI)
FULL FLAG / INPUT READY
( FULL / DRDY)
PROGRAMMABLE
ALMOST-FULL (
PRAF
)
FQV2111
FQV2101
FQV291
FQV281
FQV271
FQV261
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
DATA OUT (Q
8- 0
)
RETRANSMIT ( RET )
EMPTY FLAG / OUTPUT READY
(
EMPTY
/ QRDY )
PROGRAMMABLE ALMOST-
EMPTY ( PRAE )
HALF-FULL FLAG ( HALF )
Figure 1. Single Device Configuration Signal Flow Diagram
3F209C
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2002
Page 2 of 2
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261
FlexQ II
TM
WCLK
WEN
LOAD SDEN FWFT/SDI
Write Control
Logic
FULL / DRDY
PRAF
EMPTY
/ QRDY
Offset Register
Flag Logic
Write Pointer
PRAE
HALF
FWFT/SDI
D
8-0
Input Register
SRAM
Output Register
Output
Buffer
Q
8-0
OE
Read Pointer
Read Control
Logic
Reset
RET RCLK REN
MRST PRST
Figure 2. Device Architecture
3F209C
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2002
Page 3 of 3
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261
FlexQ II
TM
EMPTY/QRDY
FULL/DRDY
WCLK
LOAD
FWFT/SDI
MRST
RCLK
HALF
GND
PRAE
PRAF
PRST
REN
RET
50
Vcc
PIN 1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
WEN
SDEN
DC
(1)
Vcc
Vcc
GND
GND
GND
GND
GND
GND
GND
GND
GND
D8
D7
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
49
OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DNC
(2)
DNC
(2)
GND
DNC
(2)
DNC
(2)
Vcc
DNC
(2)
DNC
(2)
DNC
(2)
GND
DNC
(2)
DNC
(2)
Q8
Q7
Q6
GND
D3
D2
D1
Q4
GND
GND
D6
D5
D4
D0
Q2
Q3
TQFP - 64 (Drw No: PF-01A; Order code: PF)
STQFP - 64 (Drw No: TF-01A; Order code: TF)
Top View
NOTES:
1.
2.
DC = Don’t Care. Must be tied to GND or Vcc, cannot be left open.
DNC = Do Not Connect.
Figure 3. Device Pin Out
Vcc
Q0
Q1
Q5
3F209C
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2002
Page 4 of 4
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261
FlexQ II
Pin #
Pin Name
Pin Symbol
Input/Output
Description
Master Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
MRST
low. In Standard mode,
FULL
and
PRAF
will go high;
EMPTY
and
PRAE
will go low.
In FWFT mode,
DRDY
will go low and QRDY
will go high.
PRAF
and
PRAE
will go to the same
state as Standard mode. In both modes, all data
outputs will go low. Previous programmed
configurations will not be maintained.
Partial Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
PRST
low. In Standard mode,
FULL
and
PRAF
will go high;
EMPTY
and
PRAE
will go low. In
FWFT mode,
DRDY
will go low and QRDY will
go high.
PRAF
and
PRAE
will go to the same
state as Standard mode. In both modes, all data
outputs will go low. Previous programmed
configurations will be maintained.
Writes data into queue during low to high transitions
of WCLK if
WEN
is set to low.
Controls write operation into queue or offset registers
during low to high transition of WCLK.
During Master Reset, set
LOAD
low to select
parallel programming or default offset value of 127.
Set
LOAD
high to select serial programming or
default offset value of 1023. After Master Reset,
LOAD
controls write/read, to/from offset registers
during low to high transition of WCLK/RCLK
respectively. Use in conjunction with
WEN
/
REN
.
9 - bit wide input data bus.
Reads data from queue during low to high transitions
of RCLK if
REN
is set to low.
Controls read operation from queue or offset registers
during low to high transition of RCLK.
Setting
OE
low activates the data output drivers.
Setting
OE
high deactivates the data output drivers
(High-Z).
9 - bit wide output data bus.
Selects FWFT timing or Standard timing mode during
Master Reset. After Master Reset, if serial
programming is selected (
LOAD
= high), FWFT/SDI
is used as the serial data input for the offset registers.
Serial data is written during the low to high transition
of WCLK. Use in conjunction with
SDEN
.
TM
62
Master Reset
MRST
Input
63
Partial Reset
PRST
Input
64
1
Write Clock
Write Enable
WCLK
WEN
Input
Input
61
Load Enable
LOAD
Input
15,16,17,
18,19,20,
21,22,23
52
51
49
36,35,34,
32,31,29,
28,26,25
Data Inputs
Read Clock
Read Enable
Output Enable
D
8 - 0
RCLK
REN
Input
Input
Input
Input
OE
Data Outputs
Q
8 - 0
Output
60
First Word Fall
Through/Serial
Data Input
FWFT/SDI
Input
Table 1. Pin Descriptions
3F209C
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2002
Page 5 of 5
Microchip MCU
