FST16862 20-Bit Bus Switch
October 2001
Revised February 2002
FST16862
20-Bit Bus Switch
General Description
The Fairchild Switch FST16862 provides 20-bits of high-
speed CMOS TTL-compatible bus switching. The low On
Resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organized as a 20-bit bus switch. When OE
X
is LOW, the switch is ON and Port A is connected to Port B.
When OE
X
is HIGH, a high impedance state exists
between the A and B Ports.
Features
I
4
Ω
switch connection between two ports.
I
Minimal propagation delay through the switch.
I
Low l
CC
.
I
Zero bounce in flow-through mode.
I
Control inputs compatible with TTL level.
Ordering Code:
Order Number
FST16862QSP
FST16862MTD
Package
Number
Package Description
MQA48A 48-Lead Quarter Size Very Small Outline Package (QVSOP), JEDEC MO-154, 0.150" Wide
(Preliminary)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
© 2002 Fairchild Semiconductor Corporation
DS500702
www.fairchildsemi.com
FST16862
Connection Diagram
Truth Table
Inputs
OE
x
L
H
Inputs/Outputs
A, B
A
=
B
Z
Pin Descriptions
Pin Name
OE
x
A
B
Description
Bus Switch Enables
Bus A
Bus B
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2
FST16862
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Switch Voltage (V
S
) (Note 2)
DC Input Voltage (V
IN
) (Note 3)
DC Input Diode Current (l
IK
) V
IN
<
0V
DC Output (I
OUT
) Current
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
0.5V to
+
7.0V
Recommended Operating
Conditions
(Note 4)
Power Supply Operating (V
CC)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Input Rise and Fall Time (t
r
, t
f
)
Switch Control Input
Switch I/O
Free Air Operating Temperature (T
A
)
0 ns/V to 5 ns/V
0 ns/V to DC
-40
°
C to
+
85
°
C
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
50 mA
128 mA
±
100 mA
−
65
°
C to
+
150
°
C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
V
S
is the voltage observed/applied at either the A or B Ports across
the switch.
Note 3:
The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 4:
Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
I
I
I
OZ
R
ON
Parameter
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 6)
V
CC
(V)
4.5
4.0 - 5.5
4.0 - 5.5
5.5
0
5.5
4.5
4.5
4.5
4.0
I
CC
∆
I
CC
Quiescent Supply Current
Increase in I
CC
per Input
(Note 7)
Note 5:
Typical values are at V
CC
=
5.0V and T
A
= +25°C
Note 6:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Note 7:
Per TTL driven input, control pins only.
T
A
= −40 °C
to
+85 °C
Min
Typ
(Note 5)
Max
−1.2
2.0
0.8
±1.0
±1.0
±1.0
4
4
7
11
7
7
12
20
3
2.5
Units
V
V
V
µA
µA
µA
Ω
Ω
Ω
Ω
µA
mA
0
≤
V
IN
≤
5.5V
V
IN
=
5.5V
0
≤
A, B
≤
V
CC
V
IN
=
0V, I
IN
=
64 mA
V
IN
=
0V, I
IN
=
30 mA
V
IN
=
2.4V, I
IN
=
15 mA
V
IN
=
2.4V, I
IN
=
15 mA
V
IN
=
V
CC
or GND, I
OUT
=
0
One Input at 3.4V
Other Inputs at V
CC
or GND
Conditions
I
IN
= −18
mA
5.5
5.5
3
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FST16862
AC Electrical Characteristics
T
A
= −40 °C
to
+85 °C,
C
L
=
50pF, RU
=
RD
=
500Ω
Symbol
Parameter
V
CC
=
4.5 – 5.5V
Min
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
Propagation Delay Bus-to-Bus
(Note 8)
Output Enable Time
Output Disable Time
1.0
1.0
Max
0.25
5.0
6.0
V
CC
=
4.0V
Min
Max
0.25
5.3
6.3
ns
ns
ns
V
I
=
OPEN
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
Figures
1, 2
Figures
1, 2
Figures
1, 2
Units
Conditions
Figure
Number
Note 8:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Symbol
C
IN
C
I/O
(Note 9)
Parameter
Typ
3
6
Max
Units
pF
pF
Conditions
V
CC
=
5.0V, V
IN
=
0V
V
CC
, OE
=
5.0V, V
IN
=
0V
Control Pin Input Capacitance
Input/Output Capacitance “OFF State”
Note 9:
T
A
= +25°C,
f
=
1 Mhz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note:
Input driven by 50Ω source terminated in 50Ω
Note:
C
L
includes load and stray capacitance
Note:
Input PRR
=
1.0 MHz, t
W
=
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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4
FST16862
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Quarter Size Very Small Outline Package (QVSOP), JEDEC MO-154, 0.150" Wide
Package Number MQA48A
(Preliminary)
5
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