Preliminary
FSTU162450 Configurable 4-Bit to 20-Bit Bus Switch with
−2V
Undershoot Protection and 25Ω Series Resistors
in Outputs (Preliminary)
February 2001
Revised August 2001
FSTU162450
Configurable 4-Bit to 20-Bit Bus Switch with
−
2V Undershoot Protection
and 25
Ω
Series Resistors in Outputs (Preliminary)
General Description
The Fairchild Universal Bus Switch FSTU162450 provides
4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed CMOS
TTL-compatible bus switching. The low On Resistance of
the switch allows inputs to be connected to outputs without
adding propagation delay or generating additional ground
bounce noise.
The FSTU162450 is designed to allow “customer” configu-
ration control of the enable connections. The device can be
organized as either a five 4-bit, four 5-bit, two 10-bit or one
20-bit enable bus switch. Also achieveable are 8-bit and
16-bit enabled configurations (see Functional Description).
The device’s bit configuration is controlled through select
pin logic. (see Truth Table). When OE
x
is LOW, Port A
x
is
connected to Port B
x
. When OE
x
is HIGH, the switch is
OPEN.
The A and B Ports are protected against undershoot to
support an extended range to 2.0V below ground.
Fairchild’s integrated Undershoot Hardened Circuit
(UHC
) senses undershoot at the I/O and responds by
preventing voltage differentials from developing and turn-
ing the switch on.
Features
s
Undershoot protected to
−
2V (A and B Ports)
s
25
Ω
switch connection between two ports
s
Minimal propagation delay through the switch
s
Low l
CC
s
Zero bounce in flow-through mode
s
Control inputs compatible with TTL level
s
See Applications Notes AN-5008 and AN-5021
for UHC details
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Applications Note
Select pins S
0
, S
1
, S
2
are intended to be used as static
user configurable control pins. The AC performance of
these pins has not been characterized or tested. Switching
of these select pins during system operation may tempo-
rarily disrupt output logic states and/or enable pin controls.
Ordering Code:
Order Number
FSTU162450GX
(Note 1)
FSTU162450MTD
(Note 2)
Package Number
BGA54A
(Preliminary)
MTD56
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
BGA package available in Tape and Reel only.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
UHC is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS500423
www.fairchildsemi.com
Preliminary
FSTU162450
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Name
OE
1
, OE
2
1A, 2A
1B, 2B
S
0
, S
1
NC
Description
Bus Switch Enables
Bus A
Bus B
Bit Configuration Enables
No Connect
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
1A
3
1A
5
1A
7
1A
9
2A
1
2A
3
2A
5
2A
7
2A
9
2
1A
2
1A
4
1A
6
1A
8
1A
10
2A
2
2A
4
2A
6
2A
8
3
OE
1
1A
1
GND
GND
S
0
S
1
V
CC
2A
10
OE4
4
OE
2
1B
1
OE
5
V
CC
V
CC
GND
GND
2B
10
OE
3
5
1B
2
1B
4
1B
6
1B
8
1B
10
2B
2
2B
4
2B
6
2B
8
6
1B
3
1B
5
1B
7
1B
9
2B
1
2B
3
2B
5
2B
7
2B
9
Pin Assignment for FBGA
(Top Thru View)
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2
Preliminary
FSTU162450
Logic Diagrams
20-Bit Configuration
10-Bit Configuration
5-Bit Configuration
4-Bit Configuration
3
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Preliminary
FSTU162450
Functional Description
The device can also be configured as an 8 and 16-bit device by grounding the unused pins in the 10-bit and 20-bit configu-
rations respectively. The 8-bit configuration may also be achieved by connecting two of the 4-bit enables from the 4-bit con-
figuration together and connecting the remaining enable pin (OE) HIGH.
Truth Tables
(see Functional Description)
20-Bit Configuration (S
0
=
S
1
=
L)
Inputs
OE
1
L
H
OE
2
X
X
OE
3
X
X
OE
4
X
X
OE
5
X
X
Inputs/Outputs
1A
1-10
=
1B
1-10
, 2A
1-10
=
2B
1-10
Z
10-Bit Configuration (S
0
=
L, S
1
=
H)
Inputs
OE
1
L
L
H
H
OE
2
X
X
X
X
OE
3
X
X
X
X
OE
4
L
H
L
H
OE
5
X
X
X
X
1A
X
=
1B
X
1A
X
=
1B
X
Z
Z
Inputs/Outputs
1A
1-10
=
1B
1-10
2A
1-10
=
2B
1-10
2A
X
=
2B
X
Z
2A
X
=
2B
X
Z
5-Bit Configuration (S
0
=
H, S
1
=
L)
Inputs
OE
1
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
OE
2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
OE
3
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
OE
4
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
OE
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1A
1-5
, 1B
1-5
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
Z
Z
Z
Z
Z
Z
Z
Z
Inputs/Outputs
1A
6-10
, 1B
6-10
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
Z
Z
Z
Z
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
Z
Z
Z
Z
2A
1-5
, 2B
1-5
2A
x
=
2B
x
2A
x
=
2B
x
Z
Z
2A
x
=
2B
x
2A
x
=
2B
x
Z
Z
2A
x
=
2B
x
2A
x
=
2B
x
Z
Z
2A
x
=
2B
x
2A
x
=
2B
x
Z
Z
2A
5-10
, 2B
5-10
2A
y
=
2B
y
Z
2A
y
=
2B
y
Z
2A
y
=
2B
y
Z
2A
y
=
2B
y
Z
2A
y
=
2B
y
Z
2A
y
=
2B
y
Z
2A
y
=
2B
y
Z
2A
y
=
2B
y
Z
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4
Preliminary
FSTU162450
Truth Tables
(Continued)
4-Bit Configuration (S
0
=
S
1
=
H)
Inputs
OE
1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
OE
2
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
OE
3
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
OE
4
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
OE
5
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
1A
1-4
, 1B
1-4
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
1A
x
=
1B
x
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1A
5-8
, 1B
5-8
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
Z
Z
Z
Z
Z
Z
Z
Z
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
1A
y
=
1B
y
Z
Z
Z
Z
Z
Z
Z
Z
Inputs/Outputs
2A
3-6
, 2B
3-6
2A
x
=
2B
x
2A
x
=
2B
x
2A
x
=
2B
x
2A
x
=
2B
x
Z
Z
Z
Z
2A
x
=
2B
x
2A
x
=
2B
x
2A
x
=
2B
x
2A
x
=
2B
x
Z
Z
Z
Z
2A
x
=
2B
x
2A
x
=
2B
x
2A
x
=
2B
x
2A
x
=
2B
x
Z
Z
Z
Z
2A
x
=
2B
x
2A
x
=
2B
x
2A
x
=
2B
x
2A
x
=
2B
x
Z
Z
Z
Z
2A
7-10
, 2B
7-10
2A
y
=
2B
y
2A
y
=
2B
y
Z
Z
2A
y
=
2B
y
2A
y
=
2B
y
Z
Z
2A
y
=
2B
y
2A
y
=
2B
y
Z
Z
2A
y
=
2B
y
2A
y
=
2B
y
Z
Z
2A
y
=
2B
y
2A
y
=
2B
y
Z
Z
2A
y
=
2B
y
2A
y
=
2B
y
Z
Z
2A
y
=
2B
y
2A
y
=
2B
y
Z
Z
2A
y
=
2B
y
2A
y
=
2B
y
Z
Z
1A
9-10
, 2B
9-10
2A
1-2
, 2B
1-2
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
1A
z
=
1B
z
2A
z
=
2B
z
Z
5
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