Fremont Micro Devices
FT24C02A
Two-Wire Serial EEPROM
2K (8-bit wide)
FEATURES
Low voltage and low power operations:
FT24C02A: VCC = 1.8V to 5.5V, Industrial temperature range (-40℃ to 85℃).
Two Versions of FT24C02A:
FT24C02A-5xx: Low cost with 5 valid pins. Suitable for most application except those with
more than one EEPROM on the same IIC Bus. Details in the “Device Addressing” section.
FT24C02A-Uxx: 8 valid pins suitable for all application.
Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively).
16 bytes page write mode.
Partial page write operation allowed.
Internally organized: 256
×
8 (2K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed programming cycle (5ms maximum).
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1, 000,000 cycles endurance.
100 years data retention.
Standard 8-pin PDIP/SOIC/TSSOP/DFN and 5-pin SOT-23/TSOT-23 Pb-free packages.
DESCRIPTION
The FT24C02A is 2048 bits of serial Electrical Erasable and Programmable Read Only Memory,
commonly known as EEPROM. They are organized as 256 words of 8 bits (1 byte) each. The devices
are fabricated with proprietary advanced CMOS process for low power and low voltage applications.
These devices are available in standard 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead DFN
and 5-lead SOT-23/TSOT-23 packages. A standard 2-wire serial interface is used to address all read
and write functions. Our extended V
CC
range (1.8V to 5.5V) devices enables wide spectrum of
applications.
© 2009 Fremont Micro Devices Inc.
DS3011B-page1
FT24C02A
PIN CONFIGURATION
Pin Name
A2, A1, A0
SDA
SCL
WP
VCC
GND
NC
Pin Function
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
Write Protect
Power Supply
Ground
No-Connect
Table 1
All these packaging types come in conventional or Pb-free certified.
FT24C02A
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
FT24C02A
SCL
GND
SDA
1
2
3
4
5
WP
VCC
8L DIP
8L SOP
8L TSSOP
8L DFN
8L MSOP
SOT-23-5
TSOT-23-5
Figure 1: Package types
DS3011B-page2
© 2009 Fremont Micro Devices Inc.
FT24C02A
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature:
-40℃ to 85℃
Storage temperature:
-50℃ to 125℃
Input voltage on any pin relative to ground: -0.3V to V
CC
+ 0.3V
Maximum voltage:
8V
ESD protection on all pins:
>2000V
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the
device. Functional operation of the device at conditions beyond those listed in the specification is not
guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality.
Figure 2: Block Diagram
© 2009 Fremont Micro Devices Inc.
DS3011B-page3
FT24C02A
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of
this clock is to clock data out of the EEPROM device.
(B) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can
be wired-OR with other open-drain output devices.
(C) WRITE PROTECT (WP)
The FT24C02A devices have a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to V
IL
. Conversely all
programming functions are disabled if WP pin is connected to V
IH
or V
CC
. Read operations is not
affected by the WP pin’s input level.
MEMORY ORGANIZATION
The FT24C02A devices have 16 pages. Since each page has 16 bytes, random word addressing to
FT24C02A will require 8 bits data word addresses.
DEVICE OPERATION
(A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when
Serial clock SCL is at V
IL
. Any SDA signal transition may interpret as either a START or STOP
condition as described below.
(B) START CONDITION
With SCL
≥
V
IH
, a SDA transition from high to low is interpreted as a START condition. All valid
commands must begin with a START condition.
(C) STOP CONDITION
With SCL
≥
V
IH
, a SDA transition from low to high is interpreted as a STOP condition. All valid read
or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after
a read command. A STOP condition after page or byte write command will trigger the chip into the
STANDBY mode after the self-timed internal programming finish.
(D) ACKNOWLEDGE
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The
EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The
ACKNOWLEDGE signal occurs on the 9th serial clock after each word.
DS3011B-page4
© 2009 Fremont Micro Devices Inc.
FT24C02A
(E) STANDBY MODE
The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit
in read mode, or after completing a self-time internal programming operation.
SCL
SDA
START
Condition
Data
Valid
Data
Transition
STOP
Condition
Figure 3: Timing diagram for START and STOP conditions
START Condition
SCL
Data in
Data out
ACK
Figure 4: Timing diagram for output ACKNOWLEDGE
© 2009 Fremont Micro Devices Inc.
DS3011B-page5
