24C04A, 24C08A, 24C16A
Two-Wire Serial EEPROM
4K, 8K and 16K (8-bit wide)
FEATURES
Low voltage and low power operations:
FT24C04A/08A/16A:
V
CC
= 1.8V to 5.5V
Maximum Standby current < 1µA (typically 0.02µA and 0.06µA
@
1.8V and 5.5V respectively).
16 bytes page write mode.
Partial page write operation allowed.
Internally organized: 512
8 (4K), 1024
8 (8K), 2048
8 (16K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed Write Cycle (5ms maximum).
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1, 000,000 cycles endurance.
100 years data retention.
Industrial temperature range (-40
o
C to 85
o
C).
Standard 8-pin DIP/SOP/TSSOP/DFN/MSOP and 5-pin SOT-23/TSOT-23 Pb-free packages.
DESCRIPTION
The FT24C04A/08A/16A series are 4096/8192/16384 bits of serial Electrical Erasable and Programmable Read Only
Memory, commonly known as EEPROM. They are organized as 512/1024/2048 words of 8 bits (1 byte) each. The
devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These
devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP, 8-lead DFN, 8-lead MSOP, and 5-lead SOT-
23/TSOT-23 packages. A standard 2-wire serial interface is used to address all read and write functions. Our
extended V
CC
range (1.8V to 5.5V) devices enables wide spectrum of applications.
PIN CONFIGURATION
Pin Name
A2, A1, A0
SDA
SCL
WP
NC
Pin Function
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
Write Protect
No-Connect
© 2009 Fremont Micro Devices Inc.
DS3001M-page1
24C04A, 24C08A, 24C16A
All these packaging types come in conventional or Pb-free certified.
FT24C04A/08A/16A
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
FT24C04A/08A/16A
SCL
GND
SDA
1
2
3
4
5
WP
VCC
8L DIP
8L SOP
8L TSSOP
8L DFN
8L MSOP
SOT-23-5
TSOT-23-5
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature:
Storage temperature:
Input voltage on any pin relative to ground:
Maximum voltage:
ESD protection on all pins:
-40
o
C to 85
o
C
-50
o
C to 125
o
C
-0.3V to V
CC
+ 0.3V
8V
>2000V
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device.
Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged
exposure to extreme conditions may affect device reliability or functionality.
DS3001M-page2
© 2009 Fremont Micro Devices Inc.
24C04A, 24C08A, 24C16A
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to
clock data out of the EEPROM device.
(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to
either V
IH
or V
IL
. If left unconnected, they are internally recognized as V
IL
. FT24C04A has A0 pin as no-connect.
FT24C08A has both A0 and A1 pins as no-connect. For FT24C16A, all device address pins (A0-A2) are no-
connect.
(C) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-
OR with other open-drain output devices.
(D) WRITE PROTECT (WP)
The FT24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to V
IL
. Conversely all programming
functions are disabled if WP pin is connected to V
IH
or V
CC
. Read operations is not affected by the WP pin’s input
level.
Table A
Device
FT24C04A
FT24C08A
FT24C16A
Chip Select/Device
Address Pins Used
A2, A1
A2,
(None)
No-Connect Pins
A0
A1, A0
A2, A1, A0
Max number of similar
devices on the same bus
4
2
1
MEMORY ORGANIZATION
The FT24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes, random word
addressing to FT24C04A/08A/16A will require 9/10/11 bits data word addresses respectively.
DEVICE OPERATION
(A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock
SCL is at V
IL
. Any SDA signal transition may interpret as either a START or STOP condition as described below.
(B) START CONDITION
With SCL
V
IH
, a SDA transition from high to low is interpreted as a START condition. All valid commands
must begin with a START condition.
© 2009 Fremont Micro Devices Inc.
DS3001M-page3
24C04A, 24C08A, 24C16A
(C) STOP CONDITION
With SCL
V
IH
, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write
commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command.
A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-
timed internal programming finish.
(D) ACKNOWLEDGE
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM
acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal
occurs on the 9
th
serial clock after each word.
(E) STANDBY MODE
The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read
mode, or after completing a self-time internal programming operation.
Figure 1: Timing diagram for START and STOP conditions
SCL
SDA
START
Condition
Data
Valid
Data
Transition
STOP
Condition
Figure 2: Timing diagram for output ACKNOWLEDGE
START Condition
SCL
Data in
Data out
ACK
DS3001M-page4
© 2009 Fremont Micro Devices Inc.
24C04A, 24C08A, 24C16A
DEVICE ADDRESSING
The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read
or write command. The first four most significant bits of the device address must be 1010, which is common to all
serial EEPROM devices. The next three bits are device address bits. These three device address bits (5
th
, 6
th
and 7
th
) are
to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an
ACKNOWLEDGE signal after the 8
th
read/write bit, otherwise the chip will go into STANDBY mode. However,
matching may not be needed for some or all device address bits (5
th
, 6
th
and 7
th
) as noted below. The last or 8th bit is a
read/write command bit. If the 8th bit is at V
IH
then the chip goes into read mode. If a “0” is detected, the device enters
programming mode.
FT24C04A uses A2 (5
th
) and A1 (6
th
) device address bits. Only four FT24C04A devices can be wired-OR on the same
2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11
(b). Chip select address pin A0 is not used.
FT24C08A uses only A2 (5
th
) device address bit. Only two FT24C08A devices can be wired-OR on the same 2-wire
bus. Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select
address pins A1 and A0 are not used.
FT24C16A does not use any device address bit. Only one FT24C16A device can be used on the on 2-wire bus. Chip
Select address pins A2, A1, and A0 are not used.
WRITE OPERATIONS
(A) BYTE WRITE
A byte write operation starts when a micro-controller sends a START bit condition, follows by a proper EEPROM
device address and then a write command. If the device address bits match the chip select address, the EEPROM
device will acknowledge at the 9
th
clock cycle. The micro-controller will then send the rest of the lower 8 bits word
address. At the 18
th
cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then
transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27
th
clock cycle, the
micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed
programming mode during which all external inputs will be disabled. After a programming time of T
WC
, the byte
programming will finish and the EEPROM device will return to the STANDBY mode.
(B) PAGE WRITE
A page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along the
same page or memory row. All FT24C04A/08A/16A are organized to have 16 bytes per memory row or page.
With the same write command as the byte write, the micro-controller does not issue a STOP bit after sending the
1
st
byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27
th
clock cycle. Instead it
sends out a second 8-bit data word, with the EEPROM acknowledging at the 36
th
cycle. This data sending and
EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n
9
th
clock cycle.
After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page
programming completes after a time of T
WC
, the devices will return to the STANDBY mode.
© 2009 Fremont Micro Devices Inc.
DS3001M-page5
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