FORCE Technologies
DESCRIPTION:
The FTS256S8P is a Military 256K X 8 high-density,
low-power static RAM module comprised of two
128K x 8 monolithic SRAM’s, an advanced high-speed
CMOS decoder and decoupling capacitors surface
mounted on a co-fired ceramic substrate having
side-brazed leads.
The FTS256S8P is available in a 600-mil-wide, 32-pin
dual-in-line package that conforms to the same JEDEC
standard pin configuration as the future four megabit
monolithics.
The FTS256S8P operates from a single +5V supply
and all input and output pins are completely
TTL-compatible. The low standby power of the
FTS256S8P makes it ideal for battery-backed
applications.
2 Megabit CMOS SRAM
FTS256S8P
FEATURES:
•
262,144 by 8 Bit Configuration
•
Access Times: 85, 100, 120, 150, 200ns
•
Low Power Dissipation:
40 W (typ.) standby
375 mW (typ.) operating
•
2-Volt Data Retention
•
Fully Static Operation - No Clock or Refresh
Required
•
All inputs and Outputs are TTL-Compatible
•
600 mil, 32-pin JEDEC Standard DIP Pinout
PIN NAMES
A0 - A17
Address Inputs
I/O0 - I/O7
Data In/Out
CE
Chip Enable
WE
Write Enable
OE
Output Enable
V
DD
Power (+5V)
V
SS
Ground
N.C.
No Connect
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
This document contains information on a product that is currently released
to production at Force Technologies. Force reserves the right to
change products or specifications herein without prior notice.
1
FTS256S8P
FORCE Technologies
RECOMMENDED OPERATING RANGE
1
Symbol
Characteristic
Min. Typ.
Max. Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
2
0.8
V
C
0 +25
+70
Operating
I
-40 +25
+85
T
A
°C
Temperature
M/B -55 +25 +125
Mode
Not Selected
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
TRUTH TABLE
Pin CE WE OE I/O Pin
1
X
H X
X HIGH-Z
H X
X
X HIGH-Z
L
L
H H HIGH-Z
L
L
H
L
D
OUT
L
L
L
X
D
IN
L = LOW
Supply
Current
Standby
Standby
Active
Active
Active
X = Don’t Care
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -1.0mA 2.4
-
V
I
OL
= 2.1mA
0.4 V
CAPACITANCE
4
: T
A
= 25°C, F = 1.0MHz
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
3
Parameter
Max.
Unit
Storage Temperature
-65 to +150
°C
Temperature Under Bias
-55 to +125
°C
1
Supply Voltage
-0.5 to + 7.0
V
Input/Output Voltage
1
-0.5 to V
DD
+0.5 V
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
35
20
30
30
35
Unit
Condition
pF
V
IN
= 0V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
I
IN
I
OUT
I
CC1
I
CC2
I
SB1
I
SB2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Active
Supply Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current
Output Low Voltage
Output High Voltage
o
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
CE = V
IL
, V
IN
= V
IH
or V
IL
,
I
OUT
= 0mA
Cycle = min., Duty = 100%,
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or V
IN
≤
V
SS
+0.2V, CE
≥
V
DD
-0.2V
CE = V
IH
, V
IN
= V
IH
or V
IN
I
OUT
= 2.1mA
I
OUT
= -1.0mA
TYP.
-
-
30
75
8
3
-
-
C
Min.
Max.
Min.
I
Max.
M/B
Min.
Max.
Unit
µA
µA
mA
mA
µA
mA
V
V
-10
-10
+10
+10
50
110
200
6
0.4
-10
-10
+10
+10
50
110
400
6
0.4
-10
-10
+10
+10
60
120
1000
6
0.4
2.4
2.4
2.4
* Typical measurements made at +25 C, Cycle = min., V
DD
= 5.0V.
2
FTS256S8P
DATA RETENTION CHARACTERISTICS
Symbol
V
DR
I
CCDR2
I
CCDR3
t
CDR
t
R
Parameter
Data Retention Voltage
Data Retention Supply
Current
Data Retention Supply
Current
Chip Disable to Data
Retention Time
Recovery Time
o
FORCE Technologies
Test Conditions
CE
≥
V
DR
-0.2V
V
DR
= 2.0V
V
DR
= 3.0V
Typ.
(†)
-
4
4
-
C
Min.
Max.
Min.
I
Max.
M/B
Min.
Max.
Unit
V
µA
µA
ns
ms
2.0
5.5
90
100
2.0
5.5
170
200
2.0
5.5
700
800
0
5
0
5
0
5
t
RC
= Read Cycle Timing
† Typical measurement made at +25 C, Cycle = min., V
DD
= 5.0V.
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
* Transition measured between 0.8V and 2.2V.
0V to 3.0V
5ns *
1.5V
Figure 1.
Output Load
** Including Probe and Jig Capacitance.
+5V
1.8KΩ
Output Load
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
,
and t
WLZ
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, and t
WLZ
D
OUT
C
L
**
990Ω
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
CO
t
OV
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
Parameter
Read Cycle Time
Address Access Time
Chip Enable to Output Valid
Output Enable to Output Valid
Output Hold from Address Change
Chip Enable to Output in LOW-Z
4, 6
Output Enable to Output in LOW-Z
4, 6
Chip Enable to Output in HIGH-Z
4, 6
Output Enable to Output in HIGH-Z
4, 6
85ns
Min. Max.
100ns
Min. Max.
120ns
Min.
150ns
150
200ns
Min. Max.
Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
85
85
45
10
5
0
45
30
100
100
100
45
10
5
0
45
30
120
120
120
50
10
5
0
50
35
200
150
150
60
200
200
125
10
10
10
60
45
75
65
10
5
0
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE: Over operating ranges
7
No. Symbol
10
11
12
13
14
15
16
17
18
19
t
WC
t
AW
t
CW
t
DW
t
DH
t
WP
t
AS
t
AH
t
WHZ
t
WLZ
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Data to Write Time Overlap
Data Hold Time from Write Time
Write Pulse Width
Address Set-up Time ***
Address Hold Time
Write Enable to Output in HIGH-Z
4, 6
Write Enable to Output in LOW-Z
4, 6
85ns
Min. Max.
100ns
Min. Max.
120ns
Min.
150ns
150
115
115
50
0
85
0
5
200ns
Min. Max.
Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
80
80
35
0
55
0
5
30
5
100
90
90
35
0
65
0
5
30
5
120
105
105
40
0
75
0
5
35
5
200
190
190
100
0
125
0
5
40
100
15
5
*** Valid for both Read and Write Cycles.
3
FTS256S8P
DATA RETENTION WAVEFORM
FORCE Technologies
V
DD
4.5V
2.2V
V
DR
CE
V
SS
READ CYCLE 1:
Address Controlled. WE is HIGH. CE and OE are LOW.
ADDRESS
DATA I/O
READ CYCLE 2:
CE Controlled. WE is HIGH.
ADDRESS
CE
OE
DATA I/O
4
FTS256S8P
WRITE CYCLE 1
:
WE Controlled. OE is LOW.
FORCE Technologies
ADDRESS
CE
WE
DATA I/O
WRITE CYCLE 2:
CE Controlled. OE is HIGH.
ADDRESS
CE
WE
DATA I/O
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
5
