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Intel

IXP1240 Network Processor

Advanced Information Datasheet

Product Features

The Intel

IXP1240 Network Processor delivers high-performance processing

power and flexibility to a wide variety of LAN and telecommunications

products. Distinguishing features of the IXP1240 are the performance of ASIC

hardware along with programmability of a microprocessor.

Applications

— Multi-layer LAN Switches

— Multi-protocol Telecommunications Products

— Broadband Cable Products

— Remote Access Devices

— Intelligent PCI adapters

Industry Standard 64-bit SDRAM Interface

— Peak bandwidth of up to 928 Mbytes/sec

— Address up to 256 Mbytes of SDRAM

— Memory bandwidth improvement through

bank switching

— Read-modify-write support

— Byte aligner/merger

— Cyclic Redundancy Check (CRC)

Integrated StrongARM Core

— High-performance, low-power, 32-bit

Embedded RISC processor

— 16 Kbyte instruction cache

— 8 Kbyte data cache

— 512 byte mini-cache for data that is used once

and then discarded

— Write buffer

— Memory management unit

— Access to IXP1240 FBI Unit, PCI Unit and

SDRAM Unit via the ARM* AMBA Bus

Industry Standard 32-bit SRAM Interface

— Peak bandwidth of up to 464 Mbytes/sec

— Address up to 8 Mbytes of SRAM

— Up to 8 Mbytes FlashROM for booting

StrongARM Core

— Supports atomic push/pop operations

— Supports atomic bit set and bit clear

operations

— Memory bandwidth improvement by reduced

read/write turnaround bus cycles

Six Integrated Programmable Microengines

— Operating frequency of up to 232 MHz

— Multi-thread support of four threads per

microengine

— Single-cycle ALU and shift operations

— Zero context swap overhead

— Large Register Set: 128 General-Purpose and

128 Transfer Registers

— 2 K x 32-bit Instruction Control Store

— Access to the IXP1240 FBI Unit, PCI DMA

channels, SRAM, and SDRAM

Other Integrated Features

— Hardware Hash Unit for generation of 48- or

64-bit adaptive polynomial hash keys

— Serial UART port

— Real Time Clock

— Four general-purpose I/O pins

— Four 24-bit timers with CPU watchdog

support

— Limited JTAG Support

— 4 Kbyte Scratchpad Memory

High Bandwidth I/O Bus (IX Bus)

— 64-bit, up to 104 MHz operation

— 6.6 Gbps peak bandwidth

— 64-bit or dual 32-bit bus options

432-pin, HL-PBGA package

2 V CMOS device

— 3.3 V tolerant I/O

Integrated 32-bit, 66 MHz PCI Interface

— Supports

PCI Local Bus Specification

Revision 2.2

as a Bus Master

— 264 Mbytes/sec peak burst mode operation

— I

O* support for StrongARM Core

— Dual DMA channels

Notice:

This document contains information on products in the sampling and initial production

phases of development. The specifications are subject to change without notice. Verify with your

local Intel sales office that you have the latest datasheet before finalizing a design.

Part Number: 278405-002

August, 2001

Intel

IXP1240 Network Processor

Revision History

Date

6/8/01

8/10/01

Revision

001

002

Advance Information Release.

Release for the V2.0 SDK.

Description

Information in this document is provided in connection with Intel

products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The IXP1240 Network Processor may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries

*Other names and brands may be claimed as the property of others.

Advanced Information Datasheet

Intel

IXP1240 Network Processor

Contents

1.0

2.0

Product Description ............................................................................................................ 9

Functional Units................................................................................................................11

2.1

2.2

2.3

2.4

Conventions ........................................................................................................11

StrongARM* Core................................................................................................11

Microengines .......................................................................................................11

FBI Unit and the IX Bus.......................................................................................12

2.4.1 IX Bus Access Behavior .........................................................................12

2.4.1.1 Reset and Idle Bus Considerations ...........................................14

SDRAM and SRAM Units....................................................................................15

2.5.1 SDRAM Unit ...........................................................................................15

2.5.2 SDRAM Bus Access Behavior ...............................................................16

2.5.3 SDRAM Cyclic Redundancy Checking (CRC) .......................................17

2.5.4 SDRAM Configurations ..........................................................................18

2.5.5 SRAM Unit..............................................................................................18

2.5.5.1 SRAM Types Supported............................................................20

2.5.5.2 SRAM Configurations ................................................................20

2.5.5.3 BootROM Configurations ..........................................................20

2.5.5.4 SRAM Bus Access Behavior .....................................................21

PCI Unit ...............................................................................................................22

2.6.1 PCI Arbitration and Central Function Support ........................................22

Device Reset .......................................................................................................23

2.7.1 Hardware Initiated Reset........................................................................25

2.7.2 Software Initiated Reset .........................................................................25

2.7.3 PCI Initiated Reset .................................................................................25

2.7.4 Watchdog Timer Initiated Reset .............................................................25

Pinout Diagram....................................................................................................26

Pin Type Legend .................................................................................................27

Pin Description, Grouped by Function.................................................................28

3.3.1 Processor Support Pins..........................................................................28

3.3.2 SRAM Interface Pins ..............................................................................29

3.3.3 SDRAM Interface Pins ...........................................................................31

3.3.4 IX Bus Interface Pins..............................................................................33

3.3.5 General Purpose I/Os.............................................................................37

3.3.6 Serial Port (UART) Pins .........................................................................37

3.3.7 PCI Interface Pins ..................................................................................38

3.3.8 Power Supply Pins .................................................................................41

3.3.9 IEEE 1149.1 Interface Pins ....................................................................42

3.3.10 Miscellaneous Test Pins.........................................................................42

3.3.11 Pin Usage Summary ..............................................................................43

Pin/Signal List......................................................................................................44

Signals Listed in Alphabetical Order ...................................................................48

IX Bus Pins Function Listed by Operating Mode.................................................52

IX Bus Decode Table Listed by Operating Mode Type .......................................62

Pin State During Reset........................................................................................64

2.5

2.6

2.7

3.0

Signal Description ............................................................................................................26

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

Advanced Information Datasheet

iii

Intel

IXP1240 Network Processor

3.9

4.0

4.1

4.2

Pullup/Pulldown and Unused Pin Guidelines ...................................................... 66

Absolute Maximum Ratings ................................................................................ 67

DC Specifications................................................................................................ 70

4.2.1 Type 1 Driver DC Specifications ............................................................ 70

4.2.2 Type 2 Driver DC Specifications ............................................................ 71

4.2.3 Overshoot/Undershoot Specifications .................................................... 71

AC Specifications ................................................................................................ 72

4.3.1 Clock Timing Specifications ................................................................... 72

4.3.2 PXTAL Clock Input................................................................................. 72

4.3.3 PXTAL Clock Oscillator Specifications................................................... 73

4.3.4 PCI ......................................................................................................... 73

4.3.4.1 PCI Electrical Specification Conformance................................. 73

4.3.4.2 PCI Clock Signal AC Parameter Measurements....................... 73

4.3.4.3 PCI Bus Signals Timing............................................................. 75

4.3.5 Reset...................................................................................................... 76

4.3.5.1 Reset Timings Specification ...................................................... 76

4.3.6 IEEE 1149.1 ........................................................................................... 77

4.3.6.1 IEEE 1149.1 Timing Specifications ........................................... 78

4.3.7 IX Bus..................................................................................................... 80

4.3.7.1 FCLK Signal AC Parameter Measurements.............................. 80

4.3.7.2 IX Bus Signals Timing ............................................................... 81

4.3.7.3 IX Bus Protocol.......................................................................... 83

4.3.7.4 RDYBus................................................................................... 117

4.3.7.5 TK_IN/TK_OUT ....................................................................... 120

4.3.8 SRAM Interface .................................................................................... 120

4.3.8.1 SRAM SCLK Signal AC Parameter Measurements ................ 120

4.3.8.2 SRAM Bus Signal Timing ........................................................ 122

4.3.8.3 SRAM Bus - SRAM Signal Protocol and Timing ..................... 124

4.3.8.4 SRAM Bus - BootROM and SlowPort Timings........................ 129

4.3.8.5 SRAM Bus - BootRom Signal Protocol and Timing................. 129

4.3.8.6 SRAM Bus - Slow-Port Device Signal Protocol and Timing .... 132

4.3.9 SDRAM Interface ................................................................................. 136

4.3.9.1 SDCLK AC Parameter Measurements.................................... 136

4.3.9.2 SDRAM Bus Signal Timing ..................................................... 137

4.3.9.3 SDRAM Signal Protocol .......................................................... 138

Asynchronous Signal Timing Descriptions........................................................ 143

Package Dimensions ........................................................................................ 144

IXP1240 Package Dimensions (mm) ................................................................ 146

Electrical Specifications ................................................................................................... 67

4.3

4.4

5.0

5.1

5.2

Mechanical Specifications.............................................................................................. 144

Figures

Block Diagram....................................................................................................... 9

System Block Diagram........................................................................................ 10

SDRAM Unit Block Diagram ............................................................................... 16

SRAM Unit Block Diagram .................................................................................. 19

Reset Logic ......................................................................................................... 24

Pinout Diagram ................................................................................................... 26

Advanced Information Datasheet

型号	GCIXP1240AC	GCIXP1240AB
描述	32-BIT, 232 MHz, RISC PROCESSOR, PBGA432, PLASTIC, BGA-432	32-BIT, 200 MHz, RISC PROCESSOR, PBGA432, PLASTIC, BGA-432
是否无铅	含铅	含铅
是否Rohs认证	不符合	不符合
厂商名称	Rochester Electronics	Rochester Electronics
零件包装代码	BGA	BGA
包装说明	LBGA,	LBGA,
针数	432	432
Reach Compliance Code	unknown	unknown
地址总线宽度	32	32
位大小	32	32
边界扫描	YES	YES
最大时钟频率	232 MHz	200 MHz
外部数据总线宽度	32	32
格式	FIXED POINT	FIXED POINT
集成缓存	YES	YES
JESD-30 代码	S-PBGA-B432	S-PBGA-B432
长度	40 mm	40 mm
低功率模式	NO	NO
湿度敏感等级	1	1
端子数量	432	432
最高工作温度	70 °C	70 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LBGA	LBGA
封装形状	SQUARE	SQUARE
封装形式	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）	225	225
认证状态	COMMERCIAL	COMMERCIAL
座面最大高度	1.67 mm	1.67 mm
速度	232 MHz	200 MHz
最大供电电压	2.1 V	2.1 V
最小供电电压	1.9 V	1.9 V
标称供电电压	2 V	2 V
表面贴装	YES	YES
技术	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL
端子面层	NOT SPECIFIED	NOT SPECIFIED
端子形式	BALL	BALL
端子节距	1.27 mm	1.27 mm
端子位置	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED
宽度	40 mm	40 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC