• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command
G-Link Technology Corporation, Taiwan
Web : www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-27968078
-1-
G -LINK
GLT5640AL16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.0.1)
Pin Configurations
GLT5640AL16
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Descriptions
Pin Name
CLK
CKE
CS
RAS
CAS
WE
DQ0 ~ DQ15
Master Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data I/O
Function
Pin Name
DQM
A0-11
BA0,1
VDD
VDDQ
VSS
VSSQ
Function
DQ Mask Enable
Address Input
Bank Address
Power Supply
Power Supply for DQ
Ground
Ground for DQ
G-Link Technology Corporation, Taiwan
Web : www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-27968078
-2-
G -LINK
GLT5640AL16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.0.1)
Block Diagram
CLK
CKE
Clock
Generator
Address
Mode
Register
Row
Address
Buffer
&
Burst
counter
Bank D
Bank C
Bank B
Row Decoder
Bank A
CS
RAS
CAS
WE
Column
Address
Buffer
&
Burst
counter
Sense amplifier
Column Decoder &
Latch Circuoit
Command Decoder
DQM
Input & Output
Buffer
Latch Circuit
Control Logic
Data Control Circuit
DQ
G-Link Technology Corporation, Taiwan
Web : www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-27968078
-3-
G -LINK
GLT5640AL16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.0.1)
Pin Function
Symbol
CLK
CKE
Input
Input
Input
Function
Master Clock: Other inputs signals are referenced to the CLK rising edge
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device
input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any
bank).
Chip Select:
CS
enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when
CS
is registered HIGH.
CS
provides for external
bank selection on systems with multiple banks.
CS
is considered part of the command code.
RAS
,
CAS
,
WE
A0 - A13
Input
Command Inputs:
RAS
,
CAS
and
WE
(along with
CS
) define the command being entered.
Address Inputs: Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory
array in the respective bank. The row address is specified by A0-A11. The column address is
specified by A0-A7
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Din Mask / Output Disable : When DQM is high in burst write, Din for the current cycle is
masked. When DQM is high in burst read, Dout is disable (two - clock latency).
Data Input / Output: Data bus
Power Supply for the memory array and peripheral circuitry
Power Supply are supplied to the output buffers only
CS
Input
Input
BA0,BA1
DQM, UDQM ,
LDQM
DQ0 - DQ15
VDD, VSS
VDDQ, VSSQ
Input
Input
I/O
Supply
Supply
G-Link Technology Corporation, Taiwan
Web : www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-27968078
-4-
G -LINK
GLT5640AL16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.0.1)
Absolute Maximum Ratings
Parameter
Supply Voltage
Supply Voltage for Output
Input Voltage
Output Voltage
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Symbol
VDD
VDDQ
VI
VO
IO
PD
TOPT
TSTG
Conditions
with respect to VSS
with respect to VSSQ
with respect to VSS
with respect to VSSQ
Ta = 25 °C
Value
-0.5 to 4.6
-0.5 to 4.6
-0.5 to VDD+0.5
-0.5 to VDDQ+0.5
50
1
0 to 70
-65 to 150
Unit
V
V
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be
operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for
