GS4882, GS4982 Video Sync
Separators with 50% Sync Slicing
DATA SHEET
FEATURES
• precision 50% sync slicing
• internal color burst filter
• ±5 ns temperature stability
• superior noise immunity
• robust signal detection/output muting circuitry
• high performance dual mode input clamp
• 0.5 V to 4.0 Vpp input signal with +5 V supply
• composite, vertical, back porch, odd/even outputs
• horizontal sync output available with GS4982
• +4.5 V to +13.2 V supply voltage range
• Pb-free and Green
The GS4882 and GS4982 feature an internal color burst filter
for minimization of spurious timing information and the reduction
of external component count. The precision 50% sync slicing
feature embodied in the device provides for superior sync
extraction in the presence of noise and varying sync pulse
amplitudes. The high performance dual mode input clamp
aids in maintaining the accuracy of the internally derived 50%
sync slicing level to within ±5% as well in reducing system
start-up/recovery time. In addition, a missing pulse detector
enables the devices to quickly respond to impulse noise by
temporarily turning on a Nosync Recovery Current connected
to the dual mode input clamp. The input stage will operate with
input signal amplitudes ranging from +0.5 to +4.0V peak to
peak with a +5V supply voltage.
The GS4882 and GS4982 have robust signal detection and
output muting circuitry. Should valid video be removed from
the device input, the absence of video will be automatically
detected and all outputs muted to a logic high state after a
defined probation period. Upon the return of a valid video
signal, device outputs are enabled after receiving 8 lines of
video. An internal frequency to voltage converter also allows
the device to differentiate between valid and invalid input
signals by analyzing the horizontal scan rate of the input signal
and comparing it against the expected input signal scan rate.
The GS4882 and GS4982 are available in standard 8 pin PDIP
and SOIC packages, operate with a + 4.5 to +13.2 volt supply
voltage range and typically consume less than 6 mA of current
with a +5 V supply voltage.
DESCRIPTION
The GS4882 and GS4982 are precision sync separators for
extracting timing information from NTSC, PAL, and SECAM
video signals. The GS4882 generates noise immune and
temperature stable composite sync, vertical sync, back porch
and odd/even field signals. The GS4982 provides a horizontal
sync output for those applications requiring horizontal sync
extraction.
ORDERING INFORMATION
Part Number
GS4882-CDA
GS4882-CKA
GS4882-CTA
GS4982-CDA
GS4982-CKA
GS4982-CTA
GS4882-CKAE3
GS4982-CKAE3
Package
Type
8 pin PDIP
8 pin SOIC
8 pin SOIC Tape
8 pin PDIP
8 pin SOIC
8 pin SOIC Tape
8 pin SOIC
8 pin SOIC
Temperature
Range
0° C to 70° C
0° C to 70° C
0° C to 70° C
0° C to 70° C
0° C to 70° C
0° C to 70° C
0° C to 70° C
0° C to 70° C
Pb-Free
and Green
No
No
No
No
No
No
Yes
Yes
PIN CONNECTIONS
GS4882
COMPOSITE
SYNC OUT
COMPOSITE
VIDEO IN
VERTICAL
SYNC OUT
GROUND
1
2
3
4
8
7
6
5
V
GS4982
cc
HORIZONTAL
COMPOSITE
VIDEO IN
VERTICAL
SYNC OUT
GROUND
1
2
3
4
8
7
6
5
V
cc
ODD/EVEN
R
SET
BACK PORCH
ODD/EVEN
R
SET
BACK PORCH
Revision date: July 2004
Patent Pending.
Document No. 521 - 61 - 01
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan: Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan
Tel: +81 (03) 3349-5501
Fax: +81 (03) 3349-5505
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
VALUE/UNITS
+13.5 V
0°C
≤
T
A
≤
70°C
-65°C
≤
T
S
≤150°C
260°C
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
ELECTRICAL CHARACTERISTICS
PARAMETER
POWER
SUPPLIES
Supply Voltage
Supply Current
Signal Level
V
CC
= 5 V, R
SET
= 227 kΩ, T
A
= 25° C, C
L
=15 pF unless otherwise specified.
CONDITIONS
MIN
4.5
TYP
5.0
6
-
30
-
1.55
-
15
50
200
-
MAX
13.2
10
4.0
40
120
-
200
-
55
250
+5
UNITS
V
mA
V
µA
µs
V
Ω
dB
%
ns
ns
Outputs at Logic 1
V
CC
= 5 V
-
0.5
23
70
-
-
Nosync Recovery Current
Delay to Nosync Recovery
VIDEO
INPUT
Sync Tip Clamp Voltage
Source Impedance
Color Burst Filter
Sync Slice Level
COMPOSITE
SYNC
OUTPUT
(GS4882)
BACK
PORCH
OUTPUT
VERTICAL
SYNC
OUTPUT
HORIZONTAL
OUTPUT
(GS4982)
OUTPUT
MUTE
R
SET
REFERENCE
Delay from Video
Delay from Video
Temperature Stability
Delay
Pulse Width
Pulse Width
Serrations during vertical interval
From rising edge of sync
Attenuation at 3.58 MHz
Input Amplitude 0.5 to 2.0 Vp-p
T
A
= 25° C
T
A
= 0° C to 70° C
12
45
150
-5
400
2.0
197. 7
525
2.5
197. 7
650
3.2
197. 7
ns
µs
µs
Delay from Video
Pulse Width
Probation Period
Lock Time
R
SET
Ref. Voltage
V
OH
I
OH
= 40 µA
I
OH
= 1.6 mA
V
OL
I
OL
= -1.6 mA
340
6.0
1.2
-
1.14
4.2
2.4
-
420
8.0
2.5
8
1.24
4.6
3.4
0.3
510
10.0
5
-
1.34
-
-
0.6
ns
µs
ms
lines
V
V
V
V
LOGIC
OUTPUTS
521 - 61 - 01
2 of 7
CIRCUIT DESCRIPTION
The Block Diagrams for the GS4882 and GS4982 are shown
in Figure 6 and Figure 7, with timing diagrams for the devices
shown in Figure 8.
When presented with a composite video input signal, the
GS4882 outputs composite sync, vertical sync, back porch
and odd/even field information. The GS4982 substitutes the
composite sync output with a horizontal sync output, for those
applications requiring horizontal sync extraction.
An external resistor, R
SET
, connected to pin 6 is used to set all
timing currents in the device. For standard NTSC applications,
R
SET
should be set to 227 kΩ. The value of R
SET
for a standard
NTSC application is different for the GS4882/GS4982 line of
sync separators(R
SET
= 227 kΩ) than it is for the GS1881/
GS4881/GS4981 line of sync separators (R
SET
= 680 kΩ). This
change was made to improve jitter performance of the device.
COMPOSITE VIDEO INPUT (pin 2)
The GS4882 and GS4982 will operate with input signal
amplitudes ranging from 0.5 V to 4.0 V p-p. Composite video
is AC coupled into the device via an external coupling
capacitor connected to pin 2.
Immediately upon entering the GS4882/GS4982 the video
signal is passed to the device’s dual mode input clamp in
order to clamp the sync tip of the input video waveform to 1.55
Volts. The GS4882/GS4982’s dual mode input clamp, with
both Hard Clamp and Soft Clamp capabilities, has been
specifically designed for use in high performance sync sepa-
ration. The dual mode input clamp aids in maintaining the
accuracy of the internally derived 50% sync slicing level to
within ±5% by utilizing the Soft Clamp during steady state
operation. The device improves system start-up and impulse
noise recovery time by utilizing the device’s Hard Clamp and
Nosync Recovery Current during initial start-up and when
steady state operation has been disturbed by impulse noise.
During the clamping operation, the input video signal is
passed through the device's internal color burst filter. The
internal filter attenuates the color burst by typically >15 dB.
Figure 1 shows the typical frequency response of the internal
color burst filter.
0
-5
COMPOSITE SYNC OUTPUT (pin 1 GS4882)
The filtered video signal is then fed to a comparator which
compares it to an internally derived voltage corresponding to
the 50% point of the sync pulse amplitude.
By slicing the composite video waveform at 50% of the sync
pulse amplitude, variations in output pulse timing due to
variations in input signal amplitude are minimized. Figure 1
demonstrates the stability of output pulse timing achieved with
50% sync slicing .
With 50% Sync Slicing no Time Base Errors (TBEs)
are introduced due to variations in sync pulse amplitude.
Output pulses are always produced at t
O
+t
D
,
where
t
D
represents the delay through the device.
A
Sync Pulse No.1
SYNC PULSE AMPLITUDE
A/2
Sync Pulse No.2
50% Slice
50% Slice
t
o
Time
Fig. 2 Stability of Output Pulse Timing with Variations
in Sync Pulse Amplitude
The 50% point of sync is determined by using two identical
resistors to divide the voltage between sync tip and back
porch. The importance of precision sync tip clamping may be
appreciated here, since the sync tip voltage is used in deriving
the 50% slicing level. The back porch voltage is derived
through an internal integrate and hold circuit that is gated by
the Back Porch output signal. By integrating over the entire
back porch period, the accuracy and noise immunity of
acquired back porch voltage is greatly improved when
compared to systems using simple sample and hold
techniques.
The output of the comparator is a reproduction of the input
video signal with the active portion of video removed. This
represents the composite sync waveform presented on pin 1
of the GS4882.
The video path and composite sync slicing circuitry have been
optimized and compensated to achieve superior temperature
stability. Variations in composite sync output timing over the
commercial temperature range are less than ±5 ns.
GAIN (dB)
-15
-25
-35
0.01
0.1
1
10
FREQUENCY (MHz)
Fig. 1 Frequency Response of Internal Color Burst Filter
3 of 7
521 - 61 - 01
BACK PORCH OUTPUT (pin 5)
In an NTSC composite video signal, horizontal sync pulses
are followed by the back porch interval. The GS4882 and
GS4982 generate a negative going pulse on pin 5 during this
time. It is delayed typically 525 ns from the rising edge of sync
and has a typical width of 2.5 µs.
During the pre-equalizing, vertical sync and post equalizing
periods, composite sync doubles in frequency. The GS4882
and GS4982 maintain the back porch output at the horizontal
rate due to a Back Porch Enable (BPEN) signal, generated by
the internal Windowing Circuit, which forces back porch to be
output at the horizontal rate.
This gating circuit is also the reason for the excellent impulse
noise immunity of the back porch output as shown in Figure 3.
The GS4882 and GS4982 determine odd/even field information
by comparing vertical sync with an internally generated
horizontal sync. This output is clocked out by the falling edge
of vertical sync. The odd/even output is low during even fields
and high during odd fields.
This method of determining odd / even field information
provides for superior noise immunity. Noise during the pre-
equalizing pulses does not affect the output since the field
decision is made at the beginning of the vertical interval. This
noise immunity is displayed in Figure 4 in which an extra pre-
equalizing pulse has been added to the video input with no
negative effect on the odd/even field information.
Video
Input
Video
Input
Impulse
Noise
Impulse
Noise
Odd / Even
Output
Even
Odd
Back
Porch
Output
Fig. 4 Noise Immunity of Odd/Even Output
HORIZONTAL OUTPUT (pin 1 on GS4982)
Fig. 3 Noise Immunity of Back Porch Output
VERTICAL SYNC OUTPUT (pin 3)
The vertical sync interval is detected by integrating the
composite sync pulses. The first broad pulse causes an
internal capacitor to charge past a fixed threshold and raises
an internal vertical flag. Once the vertical flag is raised, the
positive edge of the next serration clocks out the vertical
output. When the vertical sync interval ends, the first post
equalizing pulse is unable to charge the capacitor sufficiently,
causing the vertical interval flag to go high. The rising edge of
the second post-equalizing pulse then clocks out the high flag
to end the vertical sync pulse. The vertical output is clocked
in and out and therefore is a fixed width. Since the vertical
detector is designed as a true integrator, it provides improved
noise immunity.
ODD/EVEN OUTPUT (pin 7)
NTSC, PAL and SECAM composite video standards are
interlaced video schemes and therefore have odd and even
fields. For odd fields, the first broad vertical sync pulse is
coincident with the start of horizontal, while for even fields, the
first broad vertical sync pulse starts in the middle of a
horizontal line.
As mentioned previously, the odd/even field output of the
device is generated by comparing vertical sync with an
internal horizontal sync signal. This horizontal sync signal is
a true horizontal signal (i.e. maintained during the vertical
interval) and is output on pin 1 of the GS4982. A delay of 420
ns and a width of 8.0 µs are typical for this signal. The internal
Windowing Circuit which generates horizontal sync provides
excellent impulse noise immunity as shown in Figure 5.
Video
Input
Impulse
Noise
Horizontal
Output
Fig. 5
Noise Immunity of Horizontal Sync Output
521 - 61 - 01
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SIGNAL DETECT AND OUTPUT MUTE
Internal to the GS4882 and GS4982 is a robust video signal
detection circuit. This circuit provides a reliable control signal
that will enable the sync separator outputs only when a valid
video signal is present. When the input signal is not valid, the
outputs are muted and stay in a logic high state.
The GS4882 and GS4982 differentiate between valid and in-
valid input signals by feeding the horizontal sync information
into a frequency to voltage converter. The horizontal scan rate
of the input signal is then compared to an expected input
signal horizontal scan rate. With R
SET
=227 kΩ, the sync
separator will typically define a valid input signal as one with
a horizontal frequency of 15.7 ± 4 kHz.
CLEN
+
-
Assuming that the sync separator is in steady state operation
with a valid input signal, all outputs will be enabled. Removal
of the input signal, or a significant change in the input signal
frequency, will cause an internal probation timer to be triggered.
While on probation, the sync separator outputs remain
enabled and separated sync is still produced. If a valid input
signal is not returned to the system before the probation time
expires (typically 2.5 ms), all outputs will be muted to logic
high state. Should a valid signal return during the probation
period, and eight lines be received before the probation time
expires, device outputs will remain enabled. Once device
outputs are muted, the device must receive 8 valid lines of
video at the correct horizontal frequency before the outputs
are re-enabled.
CLAMP
CLAMP
WINDOW
WINDOW
HORIZONTAL
V
SC
-
+
COMPOSITE
SYNC OUTPUT
(Pin 1)
VIDEO
INPUT
(Pin 2)
0.1µ
-
+
-
+
2
ND
ORDER
FILTER
BESSEL
BESSEL
FILTER
2
ND
ORDER
INTEGRATED
INTEGRATED
HOLD
HOLD
R
50%
POINT
SIGNAL
DETECT
R
MUTE
V
HC
FAULT
FAULT
HANDLING
HANDLING
V
SC
WINDOWING
CIRCUIT
D
Q
D
Q
ODD / EVEN
OUTPUT
(Pin 7)
G
Q
CLK Q
NO SYNC
D
V
CC
(Pin 8)
VOLTAGE
REGULATOR
VERTICAL
DETECTOR
Q
VERTICAL SYNC
OUTPUT
(PIN 3)
CLK Q
BPEN
R
SET
(Pin 6)
TIMING
CURRENTS
BACK PORCH
DETECTOR
BACK PORCH
OUTPUT
(Pin 5)
227k
0.1µ
Fig. 6
GS4882 Block Diagram
CLEN
+
-
V
SC
CLAMP
WINDOW
HORIZONTAL
-
+
HORIZONTAL
(Pin 1)
VIDEO
INPUT
(Pin 2)
0.1µ
-
+
-
+
2
ND
ORDER
BESSEL
FILTER
INTEGRATED
HOLD
R
50%
POINT
SIGNAL
DETECT
R
MUTE
V
HC
FAULT
HANDLING
V
SC
WINDOWING
CIRCUIT
D
Q
D
Q
ODD / EVEN
OUTPUT
(Pin 7)
G
Q
CLK Q
NO SYNC
D
V
CC
(Pin 8)
VOLTAGE
REGULATOR
VERTICAL
DETECTOR
Q
VERTICAL SYNC
OUTPUT
(PIN 3)
CLK Q
BPEN
R
SET
(Pin 6)
TIMING
CURRENTS
BACK PORCH
DETECTOR
BACK PORCH
OUTPUT
(Pin 5)
227k
0.1µ
Fig. 7 GS4982 Block Diagram
5 of 7
521 - 61 - 01
