GS72116ATP/J/T/U
SOJ, TSOP, FP-BGA, TQFP
Commercial Temp
Industrial Temp
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option:
–40°
to 85°C
• Package line up
J:
400 mil, 44-pin SOJ package
GJ: RoHS-compliant 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
GP: RoHS-compliant 400 mil, 44-pin TSOP Type II
package
T: 10 mm x 10 mm, 44-pin TQFP
GT: RoHS-compliant 10 mm x 10 mm, 44-pin TQFP
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid
Array package
128K x 16
2Mb Asynchronous SRAM
Pin Descriptions
Symbol
A
0
–A
16
DQ
1
–DQ
16
CE
LB
UB
WE
OE
V
DD
V
SS
NC
7, 8, 10, 12 ns
3.3 V V
DD
Center V
DD
and V
SS
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
Description
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
SOJ 128K x 16-Pin Configuration
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ6
DQ7
DQ
8
WE
A
15
A
14
A
13
A
12
A
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
A
11
NC
Top view
44-pin
SOJ
Package J
Rev: 1.09 10/2007
1/18
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin TQFP 128K x 16-Pin Configuration
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
OE UB LB
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
1
2
3
4
5
6
7
8
9
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
DQ
5
DQ
6
DQ
7
DQ
8
10
23
11
12 13 14 15 16 17 18 19 20 21 22
WE A
0
A
1
A
2
A
3
A
4
NC A
5
A
6
A
7
A
8
Package T
Fine Pitch BGA 128K x 16-Bump Configuration
1
2
3
4
5
6
A
B
C
D
E
F
G
H
LB
DQ
16
OE
UB
A
0
A
3
A
5
NC
NC
A
8
A
10
A
13
A
1
A
4
A
6
A
7
A
16
A
9
A
11
A
14
A
2
CE
DQ
2
DQ
4
DQ
5
DQ
7
WE
A
15
NC
DQ
1
DQ
3
V
DD
V
SS
DQ
14
DQ
15
V
SS
V
DD
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
NC
NC
A
12
DQ
6
DQ
8
NC
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Package U
Rev: 1.09 10/2007
2/18
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
TSOP-II 128K x 16-Pin Configuration
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ
6
DQ
7
DQ
8
WE
A
15
A14
A
13
A
12
A
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
A
11
NC
Top view
44-pin
TSOP II
Package TP
Block Diagra
m
A
0
Address
Input
Buffer
Row
Decoder
Memory Array
A
16
CE
WE
Control
OE
UB
_____
Column
Decoder
I/O Buffer
DQ
1
DQ
16
Rev: 1.09 10/2007
3/18
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Truth Table
CE
H
OE
X
WE
X
LB
X
L
UB
X
L
H
L
L
H
L
X
H
DQ
1
to DQ
8
Not Selected
Read
Read
High Z
Write
Write
Not Write, High Z
High Z
High Z
DQ
9
to DQ
16
Not Selected
Read
High Z
Read
Write
Not Write, High Z
Write
High Z
High Z
V
DD
Current
ISB
1
, ISB
2
L
L
H
L
H
L
L
X
L
L
H
I
DD
L
L
Note:
X: “H” or “L”
H
X
H
X
X
H
Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Output Voltage
Allowable power dissipation
Storage temperature
Symbol
V
DD
V
IN
V
OUT
PD
T
STG
Rating
–0.5
to +4.6
–0.5
to V
DD
+0.5
(≤ 4.6 V max.)
–0.5
to V
DD
+0.5
(≤ 4.6 V max.)
0.7
–55
to 150
Unit
V
V
V
W
o
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.09 10/2007
4/18
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/12
Input High Voltage
Input Low Voltage
Ambient Temperature,
Commercial Range
Ambient Temperature,
Industrial Range
Symbol
V
DD
V
IH
V
IL
T
Ac
T
A
I
Min
3.0
2.0
–0.3
0
–40
Typ
3.3
—
—
—
—
Max
3.6
V
DD
+0.3
0.8
70
85
Unit
V
V
V
o
C
o
C
Notes:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than
–2
V and not exceed 20 ns.
Capacitance
Parameter
Input Capacitance
Output Capacitance
Symbol
C
IN
C
OUT
Test Condition
V
IN
= 0 V
V
OUT
= 0 V
Max
5
7
Unit
pF
pF
Notes:
1. Tested at T
A
= 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Input Leakage
Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
Symbol
I
IL
I
LO
V
OH
V
OL
Test Conditions
V
IN
= 0 to V
DD
Output High Z
V
OUT
= 0 to V
DD
I
OH
=
–4mA
I
LO
= +4mA
Min
–
1 uA
–1
uA
2.4
—
Max
1 uA
1 uA
—
0.4 V
Rev: 1.09 10/2007
5/18
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
