Preliminary
GS81284Z18/36B-xxxV
119-Bump BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 8Mb, 36Mb, and 72Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-BGA package
• RoHS-compliant 119-BGA packages available
144Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–167 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS81284Z18/36-xxxV may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS81284Z18/36-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump p BGA package.
Functional Description
The GS81284Z18/36(B)-xxxV is a 144Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
-250
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
t
KQ
tCycle
Curr (x18)
Curr (x36)
3.0
4.0
480
550
6.5
6.5
370
405
-200
3.0
5.0
420
480
7.5
7.5
340
370
-167
3.4
6.0
385
430
8.0
8.0
330
360
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.00a 12/2007
1/29
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81284Z18/36B-xxxV
GS8642Z36B-xxxV Pad Out–119-Bump BGA—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQC
DQC
V
DDQ
DQC
DQC
V
DDQ
DQD
DQD
V
DDQ
DQD
DQD
A
NC
V
DDQ
2
A
E2
A
DQPC
DQC
DQC
DQC
DQC
V
DD
DQD
DQD
DQD
DQD
DQPD
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BC
V
SS
NC
V
SS
BD
V
SS
V
SS
V
SS
LBO
A
TDI
4
A
ADV
V
DD
ZQ
E1
G
A
W
V
DD
CK
NC
CKE
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BB
V
SS
NC
V
SS
BA
V
SS
V
SS
V
SS
FT
A
TDO
6
A
E3
A
DQPB
DQB
DQB
DQB
DQB
V
DD
DQA
DQA
DQA
DQA
DQPA
A
A
NC
7
V
DDQ
NC
NC
DQB
DQB
V
DDQ
DQB
DQB
V
DDQ
DQA
DQA
V
DDQ
DQA
DQA
NC
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
7 x 17 Bump BGA—14 x 22 mm
2
Body—1.27 mm Bump Pitch
Rev: 1.00a 12/2007
2/29
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81284Z18/36B-xxxV
GS8642Z18B-xxxV Pad Out–119-Bump BGA—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQB
NC
V
DDQ
NC
DQB
V
DDQ
NC
DQB
V
DDQ
DQB
NC
A
A
V
DDQ
2
A
E2
A
NC
DQB
NC
DQB
NC
V
DD
DQB
NC
DQB
NC
DQPB
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BB
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
LBO
A
TDI
4
A
ADV
V
DD
ZQ
E1
G
A
W
V
DD
CK
NC
CKE
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
BA
V
SS
V
SS
V
SS
FT
A
TDO
6
A
E3
A
DQPA
NC
DQA
NC
DQA
V
DD
NC
DQA
NC
DQA
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQA
V
DDQ
DQA
NC
V
DDQ
DQA
NC
V
DDQ
NC
DQA
NC
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
7 x 17 Bump BGA—14 x 22 mm
2
Body—1.27 mm Bump Pitch
Rev: 1.00a 12/2007
3/29
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81284Z18/36B-xxxV
GS81284Z18/36B-xxxV 119-Bump BGA Pin Description
Symbol
A
0
, A
1
An
DQ
A
DQ
B
DQ
C
DQ
D
B
A
, B
B
, B
C
, B
D
NC
CK
CKE
W
E
1
E
3
E
2
G
ADV
ZZ
FT
LBO
ZQ
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
No Connect
Clock Input Signal; active high
Clock Enable; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
BPR1999.05.18
Rev: 1.00a 12/2007
4/29
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81284Z18/36B-xxxV
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
W
H
L
L
L
L
L
L
B
A
X
L
H
H
H
L
H
B
B
X
H
L
H
H
L
H
B
C
X
H
H
L
H
L
H
B
D
X
H
H
H
L
L
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E
1
, E
2,
and E
3
) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.00a 12/2007
5/29
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
