GS81302TT07/10/19/37E-450/400/350/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
144Mb SigmaDDR
TM
-II+
Burst of 2 SRAM
450 MHz–300 MHz
1.8 V V
DD
1.8 V or 1.5 V I/O
SigmaDDR™ Family Overview
me
nd
ed
for
-450
Ne
w
The GS81302TT07/10/19/37E are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
Parameter Synopsis
-400
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
tKHKH
tKHQV
2.2 ns
2.5 ns
0.45 ns
0.45 ns
Rev: 1.00b 8/2017
No
t
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1/30
De
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SRAMs. The GS81302TT07/10/19/37E SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS81302TT07/10/19/37E SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2011, GSI Technology
GS81302TT07/10/19/37E-450/400/350/333/300
16M x 8 SigmaDDR-II+ SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
SA
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
5
NW1
NC/SA
(288Mb)
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
K
K
7
SA
NW0
SA
8
LD
SA
9
SA
10
SA
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
De
sig
Ne
w
me
nd
ed
for
SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm
2
Body—1 mm Bump Pitch
Rev: 1.00b 8/2017
No
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Notes:
1. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7.
2. Pin B5 is the expansion address.
2/30
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SA
V
SS
V
SS
NC
NC
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
ODT
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
SA
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
NC
V
DDQ
© 2011, GSI Technology
GS81302TT07/10/19/37E-450/400/350/333/300
16M x 9 SigmaDDR-II+ SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
SA
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ7
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ5
NC
DQ6
V
DDQ
NC
NC
NC
NC
NC
DQ8
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
5
NC
NC/SA
(288Mb)
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
K
K
SA
7
SA
BW0
SA
8
LD
SA
V
SS
V
SS
9
SA
10
SA
NC
NC
NC
NC
NC
NC
V
REF
DQ2
NC
NC
NC
NC
NC
TMS
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
NC
DQ0
TDI
De
sig
Ne
w
me
nd
ed
for
SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm
2
Body—1 mm Bump Pitch
Notes:
3. BW0 controls writes to DQ0 :DQ8.
4. Pin B5 is the expansion address.
Rev: 1.00b 8/2017
No
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3/30
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NC
NC
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
ODT
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
SA
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
V
DDQ
NC
© 2011, GSI Technology
GS81302TT07/10/19/37E-450/400/350/333/300
8M x 18 SigmaDDR-II+ SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
SA
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
5
BW1
NC
(288Mb)
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
K
K
7
SA
BW0
SA
8
LD
SA
9
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
De
sig
Ne
w
me
nd
ed
for
SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm
2
Body—1 mm Bump Pitch
Rev: 1.00b 8/2017
No
t
Re
co
m
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17
2. B5 is the expansion address.
4/30
n—
Di
sco
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inu
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Pr
od
u
NC
V
SS
NC
NC
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
ODT
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
SA
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
NC
V
DDQ
© 2011, GSI Technology
GS81302TT07/10/19/37E-450/400/350/333/300
4M x 36 SigmaDDR-II+ SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
SA
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
5
BW2
BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
K
K
7
BW1
BW0
SA
8
LD
SA
9
SA
NC
(288Mb)
NC
NC
NC
NC
NC
10
SA
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
De
sig
Ne
w
me
nd
ed
for
SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm
2
Body—1 mm Bump Pitch
Rev: 1.00b 8/2017
No
t
Re
co
m
Notes:
3. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35
4. B9 is the expansion address.
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NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
ODT
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
SA
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
V
DDQ
© 2011, GSI Technology
