GS815036AB-357/333/300/250
119-Bump BGA
Commercial Temp
Industrial Temp
Features
• Register-Register Late Write mode, Pipelined Read mode
• 2.5 V +200/–200 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• ZQ controlled programmable output drivers
• Dual Cycle Deselect
• Fully coherent read and write pipelines
• Byte write operation (9-bit bytes)
• Differential HSTL clock inputs, K and K
• Asynchronous output enable
• Sleep mode via ZZ
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• JEDEC-standard 119-bump BGA package
• RoHS-compliant 119-bump BGA package available
512K x 36
18Mb Register-Register Late Write SRAM
Functional Description
250 MHz–357 MHz
2.5 V V
DD
1.5 V or 1.8 V HSTL I/O
Because GS815036A is a synchronous device, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
GS815036A supports pipelined reads utilizing a rising-edge-
triggered output register. It also utilizes a Dual Cycle Deselect
(DCD) output deselect protocol.
GS815036A is implemented with high performance HSTL
technology and is packaged in a 119-bump BGA.
Family Overview
GS815036A is a 18,874,368-bit (18Mb) high performance
SRAM. This family of wide, low voltage HSTL I/O SRAMs is
designed to operate at the speeds needed to implement
economical high performance cache systems.
Mode Control
There are two mode control select pins (M1 and M2), which
allow the user to set the correct read protocol for the design.
The GS815036A supports single clock Pipeline mode, which
directly affects the two mode control select pins. In order for
the part to fuction correctly, and as specified, M1 must be tied
to V
SS
and M2 must be tied to V
DD
or V
DDQ
. This must be set
at power-up and should not be changed during operation.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Parameter Synopsis
-357
Pipeline
Cycle
tKHQV
Curr (x36)
2.8
1.4
650
-333
3.0
1.5
600
-300
3.3
1.6
550
-250
4.0
2.0
500
Unit
ns
ns
mA
Rev: 1.09 1/2013
1/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS815036AB-357/333/300/250
GS815036 Pinout—119-Bump BGA—Top View (Package B)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
2
A
A
A
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQ
D
A
NC
TMS
3
A
A
A
V
SS
V
SS
V
SS
B
C
V
SS
V
REF
V
SS
B
D
V
SS
V
SS
V
SS
M1
A
TDI
4
NC
NC
V
DD
ZQ
SS
G
NC
NC
V
DD
CK
CK
SW
A
A
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
B
B
V
SS
V
REF
V
SS
B
A
V
SS
V
SS
V
SS
M2
A
TDO
6
A
A
A
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQ
A
A
NC
NC
7
V
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
Rev: 1.09 1/2013
2/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS815036AB-357/333/300/250
GS815036A BGA Pin Description
Symbol
A
DQ
A
DQ
B
DQ
C
DQ
D
B
A
, B
B
, B
C
, B
D
NC
CK
CK
SW
G
ZZ
M1
M2
ZQ
SS
TMS
TDI
TDO
TCK
V
REF
V
DD
V
SS
V
DDQ
Type
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
Description
Address Inputs
Data Input and Output pins
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
No Connect
Clock Input Signal; active high
Clock Input Signal; active low
Write Enable; active low
Output Enable; active low
Sleep mode control; active high
Read Operation Protocol Select—Selects Register-Register read operations; must be tied low in this
device
Read Operation Protocol Select—Selects Register-Register read operations; must be tied high in this
device
FLXDrive-II™ Output Impedance Control
Synchronous Select Input
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Input Reference Voltage
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.09 1/2013
3/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS815036AB-357/333/300/250
Read Operations
Pipelined Read
A read cycle begins when the RAM captures logic 0 on SS and logic 1 on SW at the rising edge of K (and the falling edge of K).
Address inputs captured on that clock edge are propigated into the RAM, which delivers data to the input of the output registers.
The second rising edge of K fires the output registers and releases read data to the output drivers. If G is held active low, the
drivers drive the data onto the output pins. Read data is sustained on the output pins as long as G is held low or until the next rising
edge of K, at which point the outputs may update to new data or deselect, depending on what control command was registered at
the second rising edge of K.
Dual Cycle Deselect
Chip deselect (SS = logic 1) is pipelined to the same degree as read data. Therefore, a deselect command entered on the rising edge
of K is acted upon in response to the next rising edge of K.
Write Operations
Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge
of the K clock (and falling edge of the K clock).
Late Write
In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT
SRAMs.
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control
inputs are captured by the same clock edge used to capture SW.
Example of x36 Byte Write Truth Table
Function
Read
Write Byte A
Write Byte B
Write Byte C
Write Byte D
Write all Bytes
Write Abort
SW
H
L
L
L
L
L
L
Ba
X
L
H
H
H
L
H
Bb
X
H
L
H
H
L
H
Bc
X
H
H
L
H
L
H
Bd
X
H
H
H
L
L
H
FLXDrive-II™ HSTL Output Driver Impedance Control
HSTL I/O SigmaRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V
SS
via an
external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value
of the desired SRAM driver impedance. The allowable range of RQ to guarantee impedance matching with specified tolerance is
between 150Ω and 300Ω. Periodic readjustment of the output driver impedance occurs automatically because driver impedance is
affected by drifts in supply voltage and die temperature. A clock cycle counter periodically triggers an impedance evaluation,
resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the
optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires 32K start-up
clock cycles, selected or deselected, after V
DD
reaches its operating range to reach its programmed output driver impedance.
Rev: 1.09 1/2013
4/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS815036AB-357/333/300/250
Register-Register Late Write, Pipelined Read Truth Table
CK
X
↑
↑
↑
↑
↑
↑
ZZ
1
0
0
0
0
0
0
SS
X
1
0
0
0
0
0
SW
X
X
1
1
0
0
0
Bx
X
X
X
X
0
X
1
G
X
X
1
0
X
X
X
Current Operation
Sleep (Power Down) mode
Deselect
Read
Read
Write All Bytes
Write Bytes with Bx = 0
Write (Abort)
DQ
(t
n
)
Hi-Z
***
Hi-Z/
***
***
***
***
DQ
(t
n+1
)
Hi-Z
Hi-Z
Hi-Z
Q(t
n
)
D(t
n
)
D(t
n
)
Hi-Z
Notes:
1. If one or more Bx = 0, then B = “T” else B = “F”.
2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”.
3. “***” indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation.
4. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
5. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
6. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
Rev: 1.09 1/2013
5/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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