GS8160Z18/36BT-250/200/150
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Functional Description
The GS8160Z18/36BT is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
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Parameter Synopsis
-250
2.5
4.0
295
345
5.5
5.5
225
255
De
sig
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
Re
co
m
Flow Through
2-1-1-1
Rev: 1.06 9/2008
No
t
1/23
n—
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ed
Pr
od
u
-200
3.0
5.0
245
285
6.5
6.5
200
220
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8160Z18/36BT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8160Z18/36BT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
-150
3.8
6.7
200
225
7.5
7.5
185
205
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2004, GSI Technology
GS8160Z18/36BT-250/200/150
GS8160Z18BT Pinout
A
A
E
1
E
2
NC
NC
B
B
B
A
E
3
V
DD
V
SS
CK
W
CKE
G
ADV
A
A
A
A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
1M x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
FT
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
Re
co
LBO
m
A
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.06 9/2008
No
t
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
2/23
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© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36BT-250/200/150
GS8160Z36BT Pinout
A
A
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
CK
W
CKE
G
ADV
A
A
A
A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
FT
V
DD
NC
V
SS
DQ
D
DQ
D2
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
Re
co
LBO
m
A
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
Rev: 1.06 9/2008
No
t
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
3/23
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© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36BT-250/200/150
100-Pin TQFP Pin Descriptions
Symbol
A
0
, A
1
A
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
NC
DQ
A
DQ
B
DQ
C
DQ
D
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
—
I/O
I/O
I/O
I/O
In
In
In
In
In
In
Description
Address Inputs
Byte Write signal for data inputs DQ
A
; active low
Byte Write signal for data inputs DQ
B
; active low
Byte Write signal for data inputs DQ
C
; active low
Byte Write signal for data inputs DQ
D
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
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Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Linear Burst Order; active low
Core power supply
Ground
Output driver power supply
Pipeline/Flow Through Mode Control; active low
Rev: 1.06 9/2008
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Clock Input Signal
No Connect
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2004, GSI Technology
Burst Address Inputs; Preload the burst counter
Write Drivers
B
B
Data Coherency
Control Logic
B
C
B
D
E
1
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D
K
SA1
SA0
Burst
Counter
SA1’
SA0’
E
2
K
Sense Amps
Rev: 1.06 9/2008
Q
K
Write Address
Register 2
Write Address
A
0
–An
ADV
No
t
LBO
FT
K
K
Re
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for
Register 1
Match
GS8160Z18/36B NBT SRAM Functional Block Diagram
5/23
Read, Write and
Ne
w
De
sig
Memory
Array
W
D
K
Q
B
A
E
3
FT
DQa
–
DQn
Write Data
Write Data
Register 2
Register 1
n—
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K
K
CK
ct
CKE
GS8160Z18/36BT-250/200/150
© 2004, GSI Technology
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