Preliminary
GS816272CC-333/300/250/200/150
209-Bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 209-bump BGA package
• RoHS-compliant 209-bump BGA package available
256K x 72
18Mb S/DCD Sync Burst SRAMs
Flow Through/Pipeline Reads
333 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
The function of the Data Output register can be controlled by the user
via the FT mode . Holding the FT mode pin low places the RAM in
Flow Through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS816272CC is an SCD (Single Cycle Deselect) and DCD (Dual
Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read commands.
SCD SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs immediately
after the deselect command has been captured in the input registers.
DCD RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
Functional Description
Applications
The GS816272CC is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although of a
type originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main store to
networking chip set support.
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low) for
multi-drop bus applications and normal drive strength (ZQ floating or
high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Controls
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS816272CC operates on a 2.5 V or 3.3 V power supply. All
input are 3.3 V and 2.5 V compatible. Separate output power (V
DDQ
)
pins are used to decouple output noise from the internal circuits and
are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-333
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t
KQ
tCycle
Curr
t
KQ
tCycle
Curr
2.8
3.0
545
4.5
4.5
380
-300
2.8
3.3
495
5.0
5.0
345
-250
3.0
4.0
425
5.5
5.5
315
-200
3.0
5.0
345
6.5
6.5
275
-150
3.8
6.7
270
7.5
7.5
250
Unit
ns
ns
mA
ns
ns
mA
Rev: 1.02c 2/2011
1/29
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816272CC-333/300/250/200/150
GS816272C Pad Out—209-Bump BGA—Top View (Package C)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Rev 10
DQG
DQG
DQG
DQG
DQPG
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPD
DQD
DQD
DQD
DQD
2
DQG
DQG
DQG
DQG
DQPC
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPH
DQD
DQD
DQD
DQD
3
A
BC
BH
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
4
E2
BG
BD
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
ADSP
NC
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
A
A
6
ADSC
BW
E1
G
V
DD
ZQ
MCH
MCL
MCL
MCL
FT
MCL
SCD
ZZ
V
DD
LBO
A
A1
A0
7
ADV
A
NC
GW
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
A
A
8
E3
BB
BE
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
BF
BA
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
DQB
DQB
DQB
DQB
DQPF
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPA
DQE
DQE
DQE
DQE
11
DQB
DQB
DQB
DQB
DQPB
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPE
DQE
DQE
DQE
DQE
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Rev: 1.02c 2/2011
2/29
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816272CC-333/300/250/200/150
GS816272C BGA Pin Description
Symbol
A
0
, A
1
A
DQ
A,
DQP
A
DQ
B,
DQP
B
DQ
C,
DQP
C
DQ
D,
DQP
D
DQ
E,
DQP
E
DQ
F,
DQP
F
DQ
G,
DQP
G
DQ
H,
DQP
H
B
A
, B
B
, B
C
,B
D,
B
E
, B
F
, B
G
,B
H
NC
CK
GW
E
1,
E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
SCD
MCH
MCL
BW
ZQ
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
I
I
I
I
O
I
I
I
I
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
I/O
Data Input and Output pins
I
—
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D,
DQ
E
,
DQ
F
, DQ
G
, DQ
H
I/Os; active low
No Connect
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
Must Connect Low
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.02c 2/2011
3/29
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816272CC-333/300/250/200/150
GS816272C Block Diagram
Register
A0–An
D
Q
A0
D0
A1
Q0
D1
Q1
Counter
Load
A0
A1
A
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
Register
Memory
Array
Q
D
Q
36
D
36
Register
D
B
B
Q
4
Register
D
B
C
Q
Q
Register
D
Register
Q
Register
D
D
B
D
Q
Register
D
Q
36
36
Register
E
1
E
3
E
2
D
Q
36
Register
D
Q
FT
G
Power Down
Control
36
ZZ
SCD
DQx1–DQx9
Note: Only x36 version shown for simplicity.
Rev: 1.02c 2/2011
4/29
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816272CC-333/300/250/200/150
Mode Pin Functions
Mode Name
Burst Order Control
Output Register Control
Power Down Control
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
Pin Name
LBO
FT
ZZ
SCD
ZQ
State
L
H
L
H or NC
L or NC
H
L
H or NC
L
H or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.02c 2/2011
5/29
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
