GS816272C
209-Bump BGA
Commercial Temp
Industrial Temp
Features
256K x 72
18Mb Sync Burst SRAMs
200 MHz–133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Functional Description
me
nd
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for
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
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Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Parameter Synopsis
-200
t
KQ
tCycle
Curr (x72)
t
KQ
tCycle
Curr (x72)
3.0
5.0
350
6.5
6.5
225
De
sig
Applications
The GS816272C is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
No
t
Pipeline
3-1-1-1
3.3 V
Flow Through
2-1-1-1
3.3 V
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-166
3.4
6.0
300
7.0
7.0
115
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 209-bump BGA package
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS816272C is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS816272C operates on a 2.5 V or 3.3 V power supply. All
input are 3.3 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
-150
3.8
6.7
270
7.5
7.5
210
-133
4.0
7.5
245
8.5
8.5
185
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Unit
ns
ns
mA
ns
ns
mA
© 1999, GSI Technology
GS816272C
GS816272 Pad Out—209 Bump BGA—Top View (Package C)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Rev 10
DQG
DQG
DQG
DQG
DQPG
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPD
DQD
DQD
DQD
DQD
2
DQG
DQG
DQG
DQG
DQPC
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPH
DQD
DQD
DQD
DQD
3
A
BC
BH
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
4
E2
BG
BD
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
5
ADSP
NC
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
6
ADSC
BW
E1
G
7
ADV
A
NC
8
E3
BB
BE
9
A
10
DQB
DQB
DQB
DQB
DQP
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPA
DQE
DQE
DQE
DQE
11
DQB
DQB
DQB
DQB
DQPB
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPE
DQE
DQE
DQE
DQE
De
sig
V
DD
V
SS
V
DDQ
NC
A
Ne
w
V
DD
NC
A
A
A
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for
A
TMS
TDI
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Rev: 2.18 11/2005
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BA
GW
NC
V
SS
V
DD
ZQ
V
DD
V
SS
V
DDQ
V
SS
V
SS
MCH
MCL
MCL
MCL
FT
V
DD
V
SS
V
DDQ
V
SS
V
SS
V
DD
V
SS
V
DDQ
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
A
A
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
MCL
SCD
ZZ
V
DD
LBO
A
A1
A0
V
SS
V
SS
V
SS
NC
A
TCK
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
BF
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
© 1999, GSI Technology
GS816272C
GS816272 BGA Pin Description
Symbol
A
0
, A
1
An
DQ
A
DQ
B
DQ
C
DQ
D
DQ
E
DQ
F
DQ
G
DQ
H
B
A
, B
B
, B
C
,B
D,
B
E
, B
F
, B
G
,B
H
NC
CK
GW
E
1,
E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
SCD
MCH
MCL
BW
ZQ
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D,
DQ
E
,
DQ
F
, DQ
G
, DQ
H
I/Os; active low
No Connect
Clock Input Signal; active high
Chip Enable; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active high
De
sig
Burst address counter advance enable; active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
Must Connect Low
Byte Enable; active low
Address Strobe (Processor, Cache Controller); active low
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I
I
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w
Single Cycle Deselect/Dual Cycle Deselect Mode Control
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
O
I
I
I
I
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Data Input and Output pins
Output Enable; active low
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 1999, GSI Technology
GS816272C
Mode Pin Functions
Mode Name
Burst Order Control
Output Register Control
Power Down Control
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
Pin Name
LBO
FT
ZZ
SCD
ZQ
State
L
H
L
H or NC
L or NC
H
L
L
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Note:
There are pull-up devices on the ZQ, SCD, and FT pinsand a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
11
00
01
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H or NC
H or NC
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Ne
w
1st address
2nd address
3rd address
4th address
Note:
The burst counter wraps to initial state on the 5th clock.
me
nd
ed
for
01
10
Note:
The burst counter wraps to initial state on the 5th clock.
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BPR 1999.05.18
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816272C
Byte Write Truth Table
Function
Read
Read
Write byte A
Write byte B
Write byte C
Write byte D
Write byte E
Write byte F
Write byte G
Write byte H
Write all bytes
Write all bytes
GW
H
H
H
H
H
H
H
H
H
H
H
L
BW
H
L
L
L
L
L
L
L
L
L
L
X
BA
X
H
L
H
H
H
H
H
H
H
L
X
BB
X
H
H
L
H
H
H
H
H
H
L
X
BC
X
H
H
H
L
H
H
H
H
H
L
X
BD
X
H
H
H
BE
X
H
L
BF
X
H
H
L
BG
X
BH
X
H
H
H
H
L
H
H
H
L
L
X
Notes
1
1
2, 3
2, 3
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
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Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
A
, B
B
, B
C
, B
D
, B
E
, B
F
, B
G
, and/or B
H
may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “E”, “F”, “G” and “H” are only available on the x72 version.
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H
H
L
H
L
H
H
H
L
H
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
L
H
L
H
L
X
X
X
X
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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H
H
© 1999, GSI Technology
