GS8162ZxxB(B/D)-xxxV
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119- and 165-bump BGA packages
• RoHS-compliant 119- and 165-bump BGA packages
available
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–150 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Functional Description
me
nd
ed
for
The GS8162ZxxB(B/D)-xxxV is an 18Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Ne
w
Parameter Synopsis
-250
3.0
4.0
280
330
5.5
5.5
210
240
De
sig
Re
co
m
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
Flow Through
2-1-1-1
Rev: 1.03 9/2008
No
t
1/32
n—
Di
sco
nt
inu
ed
Pr
od
u
-200
3.0
5.0
230
270
6.5
6.5
185
205
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162ZxxB(B/D)-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8162ZxxB(B/D)-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump or 165-bump BGA package.
-150
3.8
6.7
185
210
7.5
7.5
170
190
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2004, GSI Technology
GS8162ZxxB(B/D)-xxxV
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
FT
DQB
DQB
DQB
DQB
DQPB
NC
LBO
2
A
A
NC
DQB
DQB
DQB
DQB
MCH
NC
NC
NC
NC
DNU
NC
NC
3
E1
E2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BB
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
NC
BA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
6
E3
CK
7
CKE
W
8
ADV
G
9
A
A
10
11
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
n—
Di
sco
nt
inu
ed
Pr
od
u
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
NC
NC
NC
NC
NC
ZQ
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
DQA
DQA
DQA
DQA
NC
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
ct
A
NC
DQPA
DQA
DQA
DQA
DQA
ZZ
NC
NC
NC
NC
NC
NC
A
Rev: 1.03 9/2008
No
t
Re
co
m
me
nd
ed
for
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Ne
w
TDI
TMS
2/32
De
sig
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162ZxxB(B/D)-xxxV
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQPC
DQC
DQC
DQC
DQC
FT
DQD
DQD
DQD
DQD
DQPD
NC
LBO
2
A
A
NC
DQC
DQC
DQC
DQC
MCH
DQD
DQD
DQD
DQD
DNU
NC
NC
3
E1
E2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BC
BD
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
BB
BA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
6
E3
CK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
7
CKE
W
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADV
G
V
SS
9
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
10
A
A
11
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
n—
Di
sco
nt
inu
ed
Pr
od
u
NC
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
DQB
DQB
DQB
DQB
ZQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
DQA
DQA
DQA
DQA
NC
A
A
ct
DQPB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
DQPA
NC
A
Rev: 1.03 9/2008
No
t
Re
co
m
me
nd
ed
for
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Ne
w
TDI
TMS
3/32
De
sig
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162ZxxB(B/D)-xxxV
GS8162ZV36B Pad Out—119-Bump BGA—Top View (Package B)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
DDQ
NC
NC
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
2
A
E
2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
3
A
A
A
V
SS
V
SS
V
SS
B
C
V
SS
NC
4
A
ADV
V
DD
ZQ
E
1
G
A
5
A
A
6
A
E
3
A
7
V
DDQ
NC
De
sig
V
SS
B
D
Ne
w
me
nd
ed
for
V
SS
V
SS
V
SS
DQP
A
A
LBO
A
TDI
Re
co
m
NC
V
DDQ
NC
TMS
U
Rev: 1.03 9/2008
No
t
4/32
n—
Di
sco
nt
inu
ed
Pr
od
u
A
NC
V
SS
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
B
DQ
B
V
SS
V
SS
B
B
V
DDQ
DQ
B
DQ
B
W
V
SS
NC
V
DD
CK
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
TDO
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
NC
NC
NC
CKE
A
1
A
0
V
DD
A
TCK
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
GS8162ZxxB(B/D)-xxxV
GS8162ZV18B Pad Out—119-Bump BGA—Top View (Package B)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
DDQ
NC
NC
DQ
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
2
A
E
2
A
NC
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
3
A
A
A
V
SS
V
SS
V
SS
B
B
V
SS
NC
4
A
5
A
6
A
7
V
DDQ
NC
De
sig
Ne
w
V
SS
NC
me
nd
ed
for
DQ
B
NC
V
SS
V
SS
V
SS
LBO
A
TDI
DQ
PB
A
A
TMS
Re
co
m
NC
NC
V
DDQ
No
t
U
Rev: 1.03 9/2008
5/32
n—
Di
sco
nt
inu
ed
Pr
od
u
ADV
V
DD
ZQ
E
1
G
A
A
E
3
A
A
NC
V
SS
DQ
PA
NC
NC
V
SS
V
SS
NC
DQ
A
DQ
A
NC
V
DDQ
DQ
A
NC
W
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
TDO
DQ
A
V
DD
NC
DQ
A
NC
DQ
A
NC
A
A
NC
V
DD
CK
NC
CKE
A
1
A
0
V
DD
NC
TCK
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
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