GS8182S08/09/18/36BD-400/375/333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
18Mb Burst of 2
SigmaSIO DDR-II
TM
SRAM
400 MHz–167 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
SigmaSIO DDR-II™ Family Overview
GS8182S08/09/18/36BD are built in compliance with the
SigmaSIO DDR-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
K clocks are routed internally to fire the output registers
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the data’s destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 1M x 18 has a 512K
addressable index).
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input register clock inputs, K and K.
The device also allows the user to manipulate the output
Parameter Synopsis
-400
tKHKH
tKHQV
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.03b 6/2010
1/37
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
2M x 8 SigmaQuad SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
D
OFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
(72Mb)
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
SA
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
NC
D6
NC
NC
Q7
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NW1
NC/SA
(288Mb)
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC/SA
(144Mb)
NW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
NC/SA
(36Mb)
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
11 x 15 Bump BGA—13 x 15 mm
2
Body—1 mm Bump Pitch
Note:
NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
Rev: 1.03b 6/2010
2/37
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
2M x 9 SigmaQuad SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
(72Mb)
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
SA
NC
NC
NC
Q5
NC
Q6
V
DDQ
NC
NC
D7
NC
NC
Q8
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NC
NC/SA
(288Mb)
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC/SA
(144Mb)
BW
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
NC/SA
(36Mb)
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
11 x 15 Bump BGA—13 x 15 mm
2
Body—1 mm Bump Pitch
Note:
BW controls writes to D0:D7.
Rev: 1.03b 6/2010
3/37
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
1M x 18 SigmaQuad SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
D
OFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
(144Mb)
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/SA
(36Mb)
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC/SA
(288Mb)
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
NC/SA
(72Mb)
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
11 x 15 Bump BGA—13 x 15 mm
2
Body—1 mm Bump Pitch
Note:
BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
Rev: 1.03b 6/2010
4/37
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
512K x 36 SigmaQuad SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
D
OFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
NC/SA
(288Mb)
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
NC/SA
(72Mb)
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW2
BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
BW1
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
NC/SA
(36Mb)
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
NC/SA
(144Mb)
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
11 x 15 Bump BGA—15 x 17 mm
2
Body—1 mm Bump Pitch
Rev: 1.03b 6/2010
5/37
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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