GS82032AT-180/166/150/133/100/66/4/
TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipelined opera-
tion
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
64K x 32
2Mb Synchronous Burst SRAM
180 MHz–66 M
3.3 V V
3.3 V and 2.5 V
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. T
Burst function need not be used. New addresses can be load
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output Register can be controlled
the user via the FT mode pin (Pin 14 in the TQFP). Holdin
the FT mode pin low places the RAM in Flow Through mo
causing output data to bypass the Data Output Register.
Holding FT high places the RAM in Pipelined mode,
activating the rising-edge-triggered Data Output Register.
Functional Description
Applications
The GS82032A is a 2,097,152-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
SCD Pipelined Reads
The GS82032A is an SCD (Single Cycle Deselect) pipeline
synchronous SRAM. DCD (Dual Cycle Deselect) versions
also available. SCD SRAMs pipeline deselect commands o
stage less than read commands. SCD RAMs begin turning
their outputs immediately after the deselect command has b
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write ena
(BW) input combined with one or more individual byte wri
signals (Bx). In addition, Global Write (GW) is available fo
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS82032A operates on a 3.3 V power supply and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to decouple output nois
from the internal circuit.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
t
KQ
I
DD
tCycle
t
KQ
I
DD
-180
5.5 ns
3.2 ns
155 mA
9.1 ns
8 ns
100 mA
-166
6 ns
3.5 ns
140 mA
10 ns
8.5 ns
90 mA
-150
6.6 ns
3.8 ns
130 mA
10.5 ns
9 ns
85 mA
-133 (-4)
7.5 ns
4 ns
115 mA
12 ns
10 ns
80 mA
-100 (-5)
10 ns
5 ns
90 mA
15 ns
12 ns
65 mA
-66 (-6)
12.5 ns
6 ns
65 mA
20 ns
18 ns
50 mA
Rev: 1.12 10/2004
1/22
© 2000, GSI Techno
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT-180/166/150/133/100/66/4/
GS82032A 100-Pin TQFP Pinout
NC
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
FT
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
64K x 32
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
A
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
CK
GW
BW
G
ADSC
ADSP
ADV
A
A
NC
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
NC
Rev: 1.12 10/2004
LBO
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
NC
2/22
© 2000, GSI Techno
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT-180/166/150/133/100/66/4/
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
NC
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
I
I
I/O
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.12 10/2004
3/22
© 2000, GSI Techno
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT-180/166/150/133/100/66/4/
GS82032A Block Diagram
A0
–
An
Register
D
Q
A0
D0
A1
Q0
D1
Q1
Counter
Load
A0
A1
A
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
Register
Memory
Array
Q
D
Q
D
Register
D
B
B
Q
32
4
32
Register
D
B
C
Q
Q
Register
D
Register
Q
Register
D
D
B
D
Q
Register
D
Q
E
1
E
2
E
3
Register
D
Q
Register
D
Q
FT
G
Power Down
Control
DQx1
–
DQx8
ZZ
Rev: 1.12 10/2004
4/22
© 2000, GSI Techno
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT-180/166/150/133/100/66/4/
Mode Pin Functions
Mode Name
Burst Order Control
Output Register Control
Power Down Control
Pin Name
LBO
FT
ZZ
State
L
H or NC
L
H or NC
L or NC
H
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Note:
There are pull-up devices on LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip w
operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
1st address
2nd address
3rd address
4th address
Interleaved Burst Sequence
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.12 10/2004
5/22
© 2000, GSI Techno
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
