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GS8342Q08/09/18/36AE-250M

165-Bump BGA

Military Temp

Features

• Military Temperature Range

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write (x36, x18, and x9) and Nybble Write (x8) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• Pin-compatible with 18Mb, 72Mb and 144Mb devices

36Mb SigmaQuad-II

Burst of 2 SRAM

Clocking and Addressing Schemes

250 MHz

1.8 V V

1.8 V and 1.5 V I/O

The GS8342Q08/09/18/36AE-250M SigmaQuad-II SRAMs

are synchronous devices. They employ two input register

clock inputs, K and K. K and K are independent single-ended

clock inputs, not differential inputs to a single differential

clock input buffer. The device also allows the user to

manipulate the output register clock quasi independently with

the C and C clock inputs. C and C are also independent single-

ended clock inputs, not differential inputs. If the C clocks are

tied high, the K clocks are routed internally to fire the output

registers instead.

Each internal read and write operation in a SigmaQuad-II B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore the address field of a

SigmaQuad-II B2 RAM is always one address pin less than the

advertised index depth (e.g., the 4M x 8 has a 2M addressable

index).

SigmaQuad™ Family Overview

The GS8342Q08/09/18/36AE-250M are built in compliance

with the SigmaQuad-II SRAM pinout standard for Separate

I/O synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342Q08/09/18/36AE-250M SigmaQuad

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Parameter Synopsis

-250M

tKHKH

tKHQV

4.0 ns

0.45 ns

Rev: 1.00a 11/2011

1/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342Q08/09/18/36AE-250M

1M x 36 SigmaQuad-II SRAM—Top View

Q27

D27

D28

Q29

Q30

D30

Doff

D31

Q32

Q33

D33

D34

Q35

TDO

Q18

Q28

D20

D29

Q21

D22

REF

Q31

D32

Q24

Q34

D26

D35

TCK

D18

D19

Q19

Q20

D21

Q22

DDQ

D23

Q23

D24

D25

Q25

Q26

DDQ

BW2

BW3

BW1

BW0

DDQ

D17

D16

Q16

Q15

D14

Q13

DDQ

D12

Q12

D11

D10

Q10

Q17

D15

Q14

D13

REF

Q11

TMS

TDI

11 x 15 Bump BGA—15 x 17 mm

Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35

2. A2, A3, and A10 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.

They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher

density device. These pins may be marked as V

, NC, or MCL by some vendors of compatible SRAMs.

Expansion Addresses

A10

72Mb

144Mb

288Mb

Rev: 1.00a 11/2011

2/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342Q08/09/18/36AE-250M

2M x 18 SigmaQuad-II SRAM—Top View

Doff

TDO

D11

Q12

D13

REF

Q15

D17

TCK

D10

Q10

Q11

D12

Q13

DDQ

D14

Q14

D15

D16

Q16

Q17

DDQ

BW1

BW0

DDQ

REF

TMS

TDI

11 x 15 Bump BGA—15 x 17 mm

Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.

2. A2, A7, and A10 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.

They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher

density device. These pins may be marked as V

, NC, or MCL by some vendors of compatible SRAMs.

Expansion Addresses

A10

72Mb

144Mb

288Mb

Rev: 1.00a 11/2011

3/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342Q08/09/18/36AE-250M

4M x 8 SigmaQuad-II SRAM—Top View

Doff

TDO

REF

TCK

DDQ

NW1

NW0

DDQ

REF

TMS

TDI

11 x 15 Bump BGA—15 x 17 mm

Body—1 mm Bump Pitch

Notes:

1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.

2. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.

They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher

density device. These pins may be marked as V

, NC, or MCL by some vendors of compatible SRAMs.

Expansion Address

72Mb

144Mb

288Mb

Rev: 1.00a 11/2011

4/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342Q08/09/18/36AE-250M

4M x 9 SigmaQuad-II SRAM — Top View

Doff

TDO

REF

TCK

DDQ

REF

TMS

TDI

11 x 15 Bump BGA—15 x 17 mm

Body—1 mm Bump Pitch

Note:

A2, A7, and B5 are reserved for future use PQ an address pin for higher density devices. They are not connected to the die on this device.

They may be left floating or be treated PQ an MCL pin (Must Connect Low) to PQsure the site will successfully accomodate a future, higher

density device. These pins may be marked PQ, V

, NC, or MCL by some vendors of compatible SRAMs.

Expansion Address

72Mb

144Mb

288Mb

Rev: 1.00a 11/2011

5/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

参数对比

与GS8342Q18AE-250MT相近的元器件有：GS8342Q09AE-250MT、GS8342Q18AE-250M、GS8342Q36AE-250M、GS8342Q36AE-250MT、GS8342Q09AE-250M、GS8342Q08AE-250MT、GS8342Q08AE-250M。描述及对比如下：

型号	GS8342Q18AE-250MT	GS8342Q09AE-250MT	GS8342Q18AE-250M	GS8342Q36AE-250M	GS8342Q36AE-250MT	GS8342Q09AE-250M	GS8342Q08AE-250MT	GS8342Q08AE-250M
描述	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
厂商名称	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40
针数	165	165	165	165	165	165	165	165
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
最长访问时间	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns
其他特性	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz
I/O 类型	SEPARATE	SEPARATE	SEPARATE	SEPARATE	SEPARATE	SEPARATE	SEPARATE	SEPARATE
JESD-30 代码	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
长度	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm
内存密度	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	33554432 bit	33554432 bit
内存集成电路类型	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM
内存宽度	18	9	18	36	36	9	8	8
功能数量	1	1	1	1	1	1	1	1
端子数量	165	165	165	165	165	165	165	165
字数	2097152 words	4194304 words	2097152 words	1048576 words	1048576 words	4194304 words	4194304 words	4194304 words
字数代码	2000000	4000000	2000000	1000000	1000000	4000000	4000000	4000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
组织	2MX18	4MX9	2MX18	1MX36	1MX36	4MX9	4MX8	4MX8
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA
封装等效代码	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
电源	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm
最大待机电流	0.3 A	0.3 A	0.3 A	0.3 A	0.3 A	0.3 A	0.3 A	0.3 A
最小待机电流	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
最大压摆率	0.8 mA	0.75 mA	0.8 mA	0.85 mA	0.85 mA	0.75 mA	0.75 mA	0.75 mA
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm