GS8342R08/09/18/36BD-400/350/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36, x18 and x9) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb
devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
36Mb SigmaDDR-II
TM
Burst of 4 SRAM
400 MHz–250 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaDDR-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 and A1 are used to initialize the pointers that control
the data multiplexer / de-multiplexer so the RAM can perform
"critical word first" operations. From an external address point
of view, regardless of the starting point, the data transfers
always follow the same linear sequence {00, 01, 10, 11} or
{01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where
the digits shown represent A1, A0).
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B4 RAMs are two address pins less than the advertised index
depth (e.g., the 4M x 8 has a 1M addressable index, and A0 and
A1 are not accessible address pins).
SigmaDDR™ Family Overview
The GS8342R08/09/18/36BD are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342R08/09/18/36BD SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342R08/09/18/36BD SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
Parameter Synopsis
-400
tKHKH
tKHQV
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.02 6/2012
1/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342R08/09/18/36BD-400/350/333/300/250
1M x 36 SigmaDDR-II SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
(144Mb)
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW2
BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
BW1
BW0
SA1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC/SA
(288Mb)
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
NC/SA
(72Mb)
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35.
2. A2, A10, and B9 are the expansion addresses.
Rev: 1.02 6/2012
2/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342R08/09/18/36BD-400/350/333/300/250
2M x 18 SigmaDDR-II SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
(72Mb)
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW1
NC/SA
(288Mb)
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC/SA
(144Mb)
BW0
SA1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17.
2. A2, A7, and B5 are the expansion addresses.
Rev: 1.02 6/2012
3/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342R08/09/18/36BD-400/350/333/300/250
4M x 9 SigmaDDR-II SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
(72Mb)
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ7
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ5
NC
DQ6
V
DDQ
NC
NC
NC
NC
NC
DQ8
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NC
NC/SA
(288Mb)
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC/SA
(144Mb)
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
NC
NC
NC
NC
NC
V
REF
DQ2
NC
NC
NC
NC
NC
TMS
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
NC
DQ0
TDI
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to
0 at the beginning of each access.
2. BW0 controls writes to DQ0:DQ8.
3. A2, A7, and B5 are the expansion addresses.
Rev: 1.02 6/2012
4/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8342R08/09/18/36BD-400/350/333/300/250
4M x 8 SigmaDDR-II SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
(72Mb)
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NW1
NC/SA
(288Mb)
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC/SA
(144Mb)
NW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to
0 at the beginning of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7.
3. A2, A7, and B5 are the expansion addresses.
Rev: 1.02 6/2012
5/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
