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GS88236BD-250

512k x 18, 256k x 36 9mb scd/dcd sync burst srams

器件类别：存储    存储   

厂商名称：GSI Technology

厂商官网：http://www.gsitechnology.com/

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参数 预览 参数对比
器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
GSI Technology
零件包装代码
BGA
包装说明
TBGA,
针数
165
Reach Compliance Code
unknown
ECCN代码
3A991.B.2.B
最长访问时间
5.5 ns
其他特性
FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码
R-PBGA-B165
JESD-609代码
e0
长度
15 mm
内存密度
9437184 bit
内存集成电路类型
CACHE SRAM
内存宽度
36
湿度敏感等级
3
功能数量
1
端子数量
165
字数
262144 words
字数代码
256000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
256KX36
封装主体材料
PLASTIC/EPOXY
封装代码
TBGA
封装形状
RECTANGULAR
封装形式
GRID ARRAY, THIN PROFILE
并行/串行
PARALLEL
峰值回流温度（摄氏度）
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
2.7 V
最小供电电压 (Vsup)
2.3 V
标称供电电压 (Vsup)
2.5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
TIN LEAD
端子形式
BALL
端子节距
1 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
13 mm
文档预览
GS88218/36BB/D-333/300/250/200/150
119- and 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 165-bump BGA packages
512K x 18, 256K x 36
9Mb SCD/DCD Sync Burst SRAMs
333 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
Functional Description
Applications
The GS88218/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
-333
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5
3.0
250
290
4.5
4.5
200
230
SCD and DCD Pipelined Reads
The GS88218/36B is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88218/36B operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 3.3 V and 2.5 V compatible.
Paramter Synopsis
-300
2.5
3.3
230
265
5.0
5.0
185
210
-250
2.5
4.0
200
230
5.5
5.5
160
185
-200
3.0
5.0
170
195
6.5
6.5
140
160
-150
3.8
6.7
140
160
7.5
7.5
128
145
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.02 10/2004
1/37
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88218/36BB/D-333/300/250/200/150
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
FT
DQB
DQB
DQB
DQB
DQB
NC
LBO
2
A
A
NC
DQB
DQB
DQB
DQB
MCL
NC
NC
NC
NC
SCD
NC
NC
3
E1
E2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BB
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
NC
BA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
E3
CK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
7
BW
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADSC
G
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
NC
NC
NC
NC
ZQ
DQA
DQA
DQA
DQA
NC
A
A
11
A18
NC
DQA
DQA
DQA
DQA
DQA
ZZ
NC
NC
NC
NC
NC
A17
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.02 10/2004
2/37
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88218/36BB/D-333/300/250/200/150
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQC
DQC
DQC
DQC
DQC
FT
DQD
DQD
DQD
DQD
DQD
NC
LBO
2
A
A
NC
DQC
DQC
DQC
DQC
MCL
DQD
DQD
DQD
DQD
SCD
NC
NC
3
E1
E2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BC
BD
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
BB
BA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
E3
CK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
7
BW
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADSC
G
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
DQB
DQB
DQB
DQB
ZQ
DQA
DQA
DQA
DQA
NC
A
A
11
NC
NC
DQB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
DQA
A17
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.02 10/2004
3/37
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88218/36BB/D-333/300/250/200/150
GS88236B Pad Out—119-Bump BGA—Top View (Package B)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
2
A
E2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
A
NC
TMS
3
A
A
A
V
SS
V
SS
V
SS
B
C
V
SS
NC
V
SS
B
D
V
SS
V
SS
V
SS
LBO
A
TDI
4
ADSP
ADSC
V
DD
ZQ
E
1
G
ADV
GW
V
DD
CK
SCD
BW
A
1
A
0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
TDO
6
A
A
A
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
NC
NC
7
V
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
PE
ZZ
V
DDQ
Rev: 1.02 10/2004
4/37
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88218/36BB/D-333/300/250/200/150
GS88218B Pad Out—119-Bump BGA—Top View (Package B)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC
V
DDQ
2
A
E2
A
NC
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
LBO
A
TDI
4
ADSP
ADSC
V
DD
ZQ
E
1
G
ADV
GW
V
DD
CK
SCD
BW
A
1
A
0
V
DD
NC
TCK
5
A
A
A
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
TDO
6
7
V
DDQ
A
A
16
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
NC
DQ
A
NC
A
A
NC
NC
NC
NC
DQ
A8
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
PE
ZZ
V
DDQ
Rev: 1.02 10/2004
5/37
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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参数对比
与GS88236BD-250相近的元器件有：GS88236BD-300、GS88236BD-200I、GS88236BD-150、GS88236BD-300I、GS88236BB-200I、GS88236BD-250I、GS88236BD-150I、GS88236BD-200。描述及对比如下：
型号 GS88236BD-250 GS88236BD-300 GS88236BD-200I GS88236BD-150 GS88236BD-300I GS88236BB-200I GS88236BD-250I GS88236BD-150I GS88236BD-200
描述 512k x 18, 256k x 36 9mb scd/dcd sync burst srams 512k x 18, 256k x 36 9mb scd/dcd sync burst srams 512k x 18, 256k x 36 9mb scd/dcd sync burst srams 512k x 18, 256k x 36 9mb scd/dcd sync burst srams 512k x 18, 256k x 36 9mb scd/dcd sync burst srams 512k x 18, 256k x 36 9mb scd/dcd sync burst srams 512k x 18, 256k x 36 9mb scd/dcd sync burst srams 512k x 18, 256k x 36 9mb scd/dcd sync burst srams 512k x 18, 256k x 36 9mb scd/dcd sync burst srams
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合
厂商名称 GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology
零件包装代码 BGA BGA BGA BGA BGA BGA BGA BGA BGA
包装说明 TBGA, TBGA, TBGA, TBGA, TBGA, BGA, TBGA, TBGA, TBGA,
针数 165 165 165 165 165 119 165 165 165
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown unknown
ECCN代码 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.A 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B
最长访问时间 5.5 ns 5 ns 6.5 ns 7.5 ns 5 ns 6.5 ns 5.5 ns 7.5 ns 6.5 ns
其他特性 FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165 R-PBGA-B119 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165
JESD-609代码 e0 e0 e0 e0 e0 e0 e0 e0 e0
长度 15 mm 15 mm 15 mm 15 mm 15 mm 22 mm 15 mm 15 mm 15 mm
内存密度 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit 9437184 bit
内存集成电路类型 CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM
内存宽度 36 36 36 36 36 36 36 36 36
湿度敏感等级 3 3 3 3 3 3 3 3 3
功能数量 1 1 1 1 1 1 1 1 1
端子数量 165 165 165 165 165 119 165 165 165
字数 262144 words 262144 words 262144 words 262144 words 262144 words 262144 words 262144 words 262144 words 262144 words
字数代码 256000 256000 256000 256000 256000 256000 256000 256000 256000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 85 °C 70 °C 85 °C 85 °C 85 °C 85 °C 70 °C
最低工作温度 - - -40 °C - -40 °C -40 °C -40 °C -40 °C -
组织 256KX36 256KX36 256KX36 256KX36 256KX36 256KX36 256KX36 256KX36 256KX36
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TBGA TBGA TBGA TBGA TBGA BGA TBGA TBGA TBGA
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 GRID ARRAY, THIN PROFILE GRID ARRAY, THIN PROFILE GRID ARRAY, THIN PROFILE GRID ARRAY, THIN PROFILE GRID ARRAY, THIN PROFILE GRID ARRAY GRID ARRAY, THIN PROFILE GRID ARRAY, THIN PROFILE GRID ARRAY, THIN PROFILE
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度（摄氏度） NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.99 mm 1.2 mm 1.2 mm 1.2 mm
最大供电电压 (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
最小供电电压 (Vsup) 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V
标称供电电压 (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
表面贴装 YES YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL COMMERCIAL
端子面层 TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD
端子形式 BALL BALL BALL BALL BALL BALL BALL BALL BALL
端子节距 1 mm 1 mm 1 mm 1 mm 1 mm 1.27 mm 1 mm 1 mm 1 mm
端子位置 BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
宽度 13 mm 13 mm 13 mm 13 mm 13 mm 14 mm 13 mm 13 mm 13 mm
高分求助，altera的srunner程序中的并口部分如何改成异步串口
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