GS88218/36BB/D-333/300/250/200/150
119- and 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 165-bump BGA packages
• RoHS-compliant 119-bump and 165-bump BGA packages
available
512K x 18, 256K x 36
9Mb SCD/DCD Sync Burst SRAMs
333 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register.
Holding FT high places the RAM in Pipeline
mode, activating the rising-edge-triggered Data Output Register.
N
ot
R
Applications
The GS88218/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no
degradation of chip performance.
ec
om
m
en
de
Paramter Synopsis
-333
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5
3.0
250
290
4.5
4.5
200
230
d
fo
r
-300
2.5
3.3
230
265
5.0
5.0
185
210
Functional Description
SCD and DCD Pipelined Reads
The GS88218/36B is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88218/36B operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 3.3 V and 2.5 V compatible.
N
-250
2.5
4.0
200
230
5.5
5.5
160
185
ew
-200
3.0
5.0
170
195
6.5
6.5
140
160
D
3.8
6.7
140
160
7.5
7.5
128
145
Flow Through
2-1-1-1
Rev: 1.04a 6/2009
1/38
es
-150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ig
n
Unit
ns
ns
mA
mA
ns
ns
mA
mA
© 2002, GSI Technology
GS88218/36BB/D-333/300/250/200/150
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
FT
DQB
DQB
DQB
DQB
DQB
NC
LBO
2
A
A
NC
DQB
DQB
DQB
DQB
MCL
NC
NC
NC
NC
SCD
NC
NC
3
E1
E2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BB
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
NC
BA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
E3
CK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
7
BW
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADSC
G
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
NC
NC
NC
NC
ZQ
DQA
DQA
DQA
DQA
NC
A
A
11
A
NC
DQA
DQA
DQA
DQA
DQA
ZZ
NC
NC
NC
NC
NC
A
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
ot
R
Rev: 1.04a 6/2009
N
ec
om
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
m
en
de
2/38
d
fo
r
N
ew
D
es
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ig
n
© 2002, GSI Technology
GS88218/36BB/D-333/300/250/200/150
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQC
DQC
DQC
DQC
DQC
FT
DQD
DQD
DQD
DQD
DQD
NC
LBO
2
A
A
NC
DQC
DQC
DQC
DQC
MCL
DQD
DQD
DQD
DQD
SCD
NC
NC
3
E1
E2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BC
BD
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
BB
BA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
E3
CK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
7
BW
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADSC
G
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
DQB
DQB
DQB
DQB
ZQ
DQA
DQA
DQA
DQA
NC
A
A
11
NC
NC
DQB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
DQA
A17
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
ot
R
Rev: 1.04a 6/2009
N
ec
om
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
m
en
de
3/38
d
fo
r
N
ew
D
es
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ig
n
© 2002, GSI Technology
GS88218/36BB/D-333/300/250/200/150
GS88236B Pad Out—119-Bump BGA—Top View (Package B)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
V
DDQ
NC
NC
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
2
A
E2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
3
A
A
A
V
SS
V
SS
V
SS
B
C
4
ADSP
ADSC
V
DD
ZQ
E
1
G
5
A
A
A
V
SS
V
SS
V
SS
B
B
6
A
A
A
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
NC
NC
7
V
DDQ
NC
ew
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
TDO
de
d
V
SS
NC
fo
r
GW
V
DD
CK
SCD
BW
A
1
A
0
V
DD
A
TCK
ADV
N
en
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
B
D
V
SS
V
SS
V
SS
LBO
A
TDI
m
om
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
ec
ot
R
DQP
D
A
NC
TMS
N
R
T
U
Rev: 1.04a 6/2009
4/38
D
es
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
PE
ZZ
V
DDQ
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ig
n
NC
© 2002, GSI Technology
GS88218/36BB/D-333/300/250/200/150
GS88218B Pad Out—119-Bump BGA—Top View (Package B)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
V
DDQ
NC
NC
DQ
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
2
A
E2
A
NC
DQ
B
NC
DQ
B
NC
V
DD
3
A
A
A
V
SS
V
SS
V
SS
B
B
4
ADSP
ADSC
V
DD
ZQ
E
1
G
ADV
GW
5
A
A
A
V
SS
V
SS
V
SS
NC
6
A
A
A
16
DQP
A
NC
7
V
DDQ
NC
ew
NC
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
TDO
NC
NC
NC
A
A
NC
N
V
SS
NC
fo
r
V
DD
CK
SCD
BW
A
1
A
0
V
DD
NC
TCK
d
en
de
DQ
B
NC
V
SS
NC
V
SS
V
SS
V
SS
LBO
A
TDI
m
DQ
B
om
V
DDQ
DQ
B
NC
NC
NC
V
DDQ
DQ
B
NC
DQP
B
A
A
TMS
ec
ot
R
N
R
T
U
Rev: 1.04a 6/2009
5/38
D
DQ
A
DQ
A
V
DD
DQ
A
DQ
A
es
NC
DQ
A8
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
PE
ZZ
V
DDQ
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ig
n
NC
© 2002, GSI Technology
