Preliminary
GS882V37BB-333/300/275/250/225/200
119-Bump BGA
Commercial Temp
Industrial Temp
Features
256K x 36
9Mb SCD/DCD Sync Burst SRAM
Byte Write and Global Write
333 MHz–200 MHz
1.8 V V
DD
1.8 V I/O
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump BGA package
configure this SRAM for either mode of operation using the SCD
mode input.
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
Pipeline
3-1-1-1
1.8 V
t
KQ
tCycle
Curr
(x36)
-333 -300 -275 -250 -225 -200 Unit
2.0 2.2 2.3 2.3 2.5 2.7 ns
3.0 3.3 3.6 4.0 4.4 5.0 ns
435
395
360
330 300 270 mA
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Functional Description
Applications
The GS882V37BB is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Core and Interface Voltages
The GS882V37BB operates on a 1.8 V power supply. All inputs
are 1.8 V compatible. Separate output power (V
DDQ
) pins are used
to decouple output noise from the internal circuits and are 1.8 V
compatible.
Controls
SCD and DCD Pipelined Reads
The GS882V37BB is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
Rev: 1.00 1/2003
1/26
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS882V37BB-333/300/275/250/225/200
GS882V37B Pad Out
119 Bump BGA
—
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C4
DQ
C3
V
DDQ
DQ
C2
DQ
C1
V
DDQ
DQ
D1
DQ
D2
V
DDQ
DQ
D3
DQ
D4
NC
NC
V
DDQ
2
A
6
NC
A
5
DQ
C9
DQ
C8
DQ
C7
DQ
C6
DQ
C5
V
DD
DQ
D5
DQ
D6
DQ
D7
DQ
D8
DQ
D9
A
2
NC
TMS
3
A
7
A
4
A
3
V
SS
V
SS
V
SS
B
C
V
SS
NC
V
SS
B
D
V
SS
V
SS
V
SS
LBO
A
10
TDI
4
ADSP
ADSC
V
DD
ZQ
E
1
G
ADV
GW
V
DD
CK
SCD
BW
A
1
A
0
V
DD
A
11
TCK
5
A
8
A
15
A
14
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
V
DDQ
/
DNU
A
12
TDO
6
A
9
A
17
A
16
DQ
B9
DQ
B8
DQ
B7
DQ
B6
DQ
B5
V
DD
DQ
A5
DQ
A6
DQ
A7
DQ
A8
DQ
A9
A
13
NC
NC
7
V
DDQ
NC
NC
DQ
B4
DQ
B3
V
DDQ
DQ
B2
DQ
B1
V
DDQ
DQ
A1
DQ
A2
V
DDQ
DQ
A3
DQ
A4
PE
ZZ
V
DDQ
Rev: 1.00 1/2003
2/26
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS882V37BB-333/300/275/250/225/200
GS882V37B (PE = 0) Block Diagram
Register
A0–An
D
Q
A0
D0
A1
Q0
D1
Q1
Counter
Load
A0
A1
A
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
Register
Memory
Array
Q
D
Q
36
D
36
Register
D
B
B
Q
4
4
Register
D
B
C
Q
Register
D
Q
Register
D
B
D
Q
Register
4
Register
D
Q
36
36
36
E
1
Register
D
Q
36
32
Parity
Encode
4
Parity
Compare
36
Register
D
Q
1
G
Power Down
Control
ZZ
SCD
DQx1–DQx9
NC
D
NC
Note: Only x36 version shown for simplicity.
Rev: 1.00 1/2003
3/26
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q
Q
D
Register
Preliminary
GS882V37BB-333/300/275/250/225/200
GS882V37B (PE = 1) x32 Mode Block Diagram
Register
A0–An
D
Q
A0
D0
A1
Q0
D1
Q1
Counter
Load
A0
A1
A
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
Register
Memory
Array
Q
D
Q
36
D
36
4
Parity
Encode
32
Register
D
B
B
Q
4
Register
D
B
C
Q
Q
Register
D
Register
Q
Register
D
D
B
D
Q
Register
D
Q
32
36
Register
36
E
1
Register
D
Q
D
Q
4
32
Register
32
Parity
Encode
4
Parity
Compare
32
Register
D
Q
D
Q
1
G
Power Down
Control
ZZ
SCD
DQx1–DQx9
NC
NC
Note: Only x36 version shown for simplicity.
Rev: 1.00 1/2003
4/26
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS882V37BB-333/300/275/250/225/200
Mode Pin Functions
Mode Name
Burst Order Control
Power Down Control
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
Pin
Name
LBO
ZZ
SCD
ZQ
State
L
H
L or NC
H
L
H or NC
L
H or NC
Function
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Note:
Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte.
Burst Counter Sequences
Linear Burst Sequence
I
nterleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
01
10
11
00
10
11
00
01
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00 1/2003
5/26
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
