DQ25–DQ32. Data I/O are high-impedance if either of these inputs are LOW, conditioned
by BWE being LOW.
Write Enable:
This active LOW input gates byte Write operations and must meet the set-up
and hold times around the rising edge of CLK.
Global Write:
This active LOW input allows a full 32-bit Write to occur independent of the
BWE and BWn lines and must meet the set-up and hold times around the rising edge of
CLK.
Clock:
This signal registers the addresses, data, chip enables, Write control and burst
control inputs on its rising edge. All synchronous inputs must meet set-up and hold times
around the clock’s rising edge.
Chip Enable:
This active LOW input is used to enable the device and to gate ADSP.
Chip Enable:
This active LOW input is used to enable the device.
Chip Enable:
This active HIGH input is used to enable the device.
Output Enable:
This active LOW asynchronous input enables the data output drivers.
Address Advance:
This active LOW input is used to control the internal burst counter.
A HIGH on this pin generates wait cycle (no address advance).
Address Status Processor:
This active LOW input, along with CE being LOW, causes a
new external address to be registered and a Read cycle is initiated using the new address.
Address Status Controller:
This active LOW input causes device to be de-selected or
selected along with new external address to be registered. A Read or Write cycle is initiated
depending upon Write control inputs.
Mode:
This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC
or HIGH on this pin selects Interleaved Burst.
Snooze:
This active HIGH input puts the device in low power consumption standby mode.
For normal operation, this input has to be either LOW or NC (No Connect).
Data Inputs/Outputs:
First Byte is DQ1–DQ8. Second Byte is DQ9–DQ16. Third Byte is
DQ17–DQ24. Fourth Byte is DQ25–DQ32. Input data must meet set-up and hold times
around the rising edge of CLK.
Power Supply:
+3.3V –5% to +10%. Pin 14 does not have to be connected directly to V
CC
as long as it is greater than V
IH
.
Ground:
GND
Output Buffer Supply:
+3.3V –5% to +10%. For 2.5V I/O: 2.375V to V
CC
.
Output Buffer Ground:
GND
No Connect:
These signals are not internally connected.
BW1, BW2,
BW3, BW4
BWE
GW
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Static
Input-
Asynchronous
Input/
Output
Supply
Ground
I/O Supply
I/O Ground
-
CLK
CE
CE2
CE2
OE
ADV
ADSP
ADSC
MODE
ZZ
DQ1–
DQ32
V
CC
V
SS
V
CCQ
V
SSQ
NC
Burst Address Table (MODE = NC/V
CC
)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A00
A...A11
A...A10
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Page 4 of 12
Document #: 38-05153 Rev. *A
CY7C1340A/
GVT71128C32
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
H
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2 CE2 ADSP
X
X
H
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC
L
X
X
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Partial Truth Table for Read/Write
FUNCTION
Read
Read
Write one byte
Write all bytes
Write all bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
BW1
X
H
L
L
X
BW2
X
H
H
L
X
BW3
X
H
H
L
X
BW4
X
H
H
L
X
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW. Write = L means [BWE + BW1*BW2*BW3*BW4]*GW equals LOW. Write = H means
[BWE + BW1*BW2*BW3*BW4]*GW equals HIGH.
3. BW1 enables Write to DQ1–DQ8. BW2 enables Write to DQ9–DQ16. BW3 enables Write to DQ17–DQ24. BW4 enables Write to DQ25–DQ32.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW–HIGH) of CLK.
5. Suspending burst generates Wait cycle.
6. For a Write operation following a Read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a Read cycle at the L–H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L–H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
