PRELIMINARY
GALVANTECH
, INC.
ASYNCHRONOUS
SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Fast access times: 10, 12, 15and 20ns
Fast OE# access times: 5, 6, 7 and 8ns
Single +5V +10% power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise immunity
Easy memory expansion with CE# and OE# options
Automatic CE# power down
High-performance, low-power consumption, CMOS
double-poly, double-metal process
Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil
TSOP
GVT7264A18
REVOLUTIONARY PINOUT 64K X 18
64K x 18 SRAM
WITH SINGLE CHIP ENABLE
REVOLUTIONARY PINOUT
GENERAL DESCRIPTION
The GVT7264A18 is organized as a 65,536 x 18 SRAM
using a four-transistor memory cell with a high performance,
silicon gate, low-power CMOS process. Galvantech SRAMs
are fabricated using double-layer polysilicon, double-layer
metal technology.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable (CE#), separate byte
enable controls (BLE# and BHE#) and output enable (OE#)
with this organization.
The device offers a low power standby mode when chip
is not selected. This allows system designers to meet low
standby power requirements.
OPTIONS
• Timing
10ns access
12ns access
15ns access
20ns access
• Packages
44-pin SOJ (400 mil)
44-pin TSOP (400 mil)
• Power consumption
Standard
Low
•
• Temperature
Commercial
Industrial
•
MARKING
-10
-12
-15
-20
PIN ASSIGNMENT
44-Pin SOJ
44-Pin TSOP
A4
A3
A2
A1
A0
CE#
DQ1
DQ2
DQ3
DQ4
VCC
VSS
DQ5
DQ6
DQ7
DQ8
DQ9
WE#
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
J
TS
None
L
None
I
(
0°C
to
70°C)
(
-40°C
to
85°C)
Part Number Examples
PART NO.
Pkg
GVT7264A18J-10L
44-pin SOJ (400 mil)
A5
A6
A7
OE#
BHE#
BLE#
DQ18
DQ17
DQ16
DQ15
VSS
VCC
DQ14
DQ13
DQ12
DQ11
DQ10
NC
A8
A9
A10
A11
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699
Rev. 6/96
Galvantech, Inc. reserves the right to change
products or specifications without notice.
PRELIMINARY
GALVANTECH
, INC.
GVT7264A18
REVOLUTIONARY PINOUT 64K X 18
FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
BLE#
A0
DQ1
ROW DECODER
ADDRESS BUFFER
I/O CONTROL
MEMORY ARRAY
512 ROWS X 128 X 18
COLUMNS
DQ9
DQ10
DQ18
A15
COLUMN DECODER
POWER
DOWN
CE#
BHE#
WE#
OE#
June 14, 1996
Rev. 6/96
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
PRELIMINARY
GALVANTECH
TRUTH TABLE
MODE
LOW BYTE READ (DQ1-DQ9)
HIGH BYTE READ (DQ10-DQ18)
WORD READ (DQ1-DQ18)
LOW BYTE WRITE (DQ1-DQ9)
HIGH BYTE WRITE (DQ10-DQ18)
WORD WRITE (DQ1-DQ18)
OUTPUT DISABLE
STANDBY
, INC.
GVT7264A18
REVOLUTIONARY PINOUT 64K X 18
CE#
L
L
L
L
L
L
L
L
H
WE#
H
H
H
L
L
L
X
H
X
OE#
L
L
L
X
X
X
X
H
X
BLE#
L
H
L
L
H
L
H
X
X
BHE#
H
L
L
H
L
L
H
X
X
DQ1-
DQ9
Q
HIGH-Z
Q
D
HIGH-Z
D
HIGH-Z
HIGH-Z
HIGH-Z
DQ10-
DQ18
HIGH-Z
Q
Q
HIGH-Z
D
D
HIGH-Z
HIGH-Z
HIGH-Z
POWER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
STANDBY
PIN DESCRIPTIONS
SOJ & TSOP
Pin Numbers
5, 4, 3, 2, 1, 44, 43,
42, 26, 25, 24, 23,
22, 21, 20, 19
18
6
SYMBOL
A0-A15
TYPE
Input
DESCRIPTION
Addresses Inputs: These inputs determine which cell is addressed.
WE#
CE#
Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW
for a WRITE cycle and HIGH for a READ cycle.
Chip Enable: This active LOW input is used to enable the device. When CE# is LOW, the
chip is selected. When CE# is HIGH, the chip is disabled and automatically goes into
standby power mode.
Byte Enable: These active LOW inputs allow individual bytes to be written or read. When
BLE# is LOW, the data is written to or read from the lower byte (DQ1-DQ9). When BHE# is
LOW, the data is written to or read from the higher byte (DQ10-DQ18).
Output Enable: This active LOW input enables the output drivers.
Input
39, 40
BLE#, BHE#
Input
41
7, 8, 9, 10, 13, 14, 15,
16, 17, 28, 29, 30,
31, 32, 35, 36, 37, 38
11, 33
12, 34
OE#
DQ1-DQ18
Input
Input/Output SRAM Data I/O: Data inputs and data outputs. Lower byte is DQ1-DQ9 and upper byte is
DQ10-DQ18.
Supply
Supply
Power Supply: 5V
+
10%
Ground
VCC
VSS
June 14, 1996
Rev. 6/96
3
Galvantech, Inc. reserves the right to change products or specifications without notice.
PRELIMINARY
GALVANTECH
, INC.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V
V
IN
..........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ..........................-55
o
C to +125
o
Junction Temperature .....................................................+125
o
Power Dissipation ...........................................................1.2W
Short Circuit Output Current .......................................50mA
GVT7264A18
REVOLUTIONARY PINOUT 64K X 18
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(All Temperature Ranges; VCC = 5V +10% unless otherwise noted)
DESCRIPTION
Input High (Logic 1) voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
CONDITIONS
SYMBOL
V
IH
V
Il
IL
I
IL
O
V
OH
V
OL
VCC
MIN
2.2
-0.5
-5
-5
2.4
4.5
MAX
VCC+1
0.8
5
5
UNITS
V
V
uA
uA
V
V
V
NOTES
1, 2
1, 2
0V < V
IN
< VCC
Output(s) disabled,
0V < V
OUT
< VCC
I
OH
= -4.0mA
I
OL
= 8.0mA
0.4
5.5
1
1
1
DESCRIPTION
Power Supply
Current: Operating
TTL Standby
CMOS Standby
CONDITIONS
Device selected; CE# < V
IL
; VCC =MAX;
f=f
MAX
; outputs open
CE# >V
IH
; VCC = MAX; f=f
MAX
CE1# >VCC -0.2; VCC = MAX;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0
SYM
Icc
I
SB1
I
SB2
TYP
150
20
0.75
POWER
-10
380
340
60
45
5
5
-12
330
300
55
40
5
5
-15
270
230
50
35
5
5
-20
210
180
40
30
7
7
UNITS
NOTES
mA
mA
mA
3, 14
14
14
standard
low
standard
low
standard
low
CAPACITANCE
DESCRIPTION
Input Capacitance
Input/Output Capacitance (DQ)
CONDITIONS
T
A
= 25
o
C; f = 1 MHz
VCC = 5V
SYMBOL
C
I
C
I/O
MAX
6
8
UNITS
pF
pF
NOTES
4
4
June 14, 1996
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 6/96
PRELIMINARY
GALVANTECH
, INC.
GVT7264A18
REVOLUTIONARY PINOUT 64K X 18
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 5V
+10%
)
DESCRIPTION
READ Cycle
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Output Enable access time
Output Enable to output in Low-Z
Output Enable to output in High-Z
Byte Enable access time
Byte Enable to output in Low-Z
Byte disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
WRITE Cycle
WRITE cycle time
Chip Enable to end of write
Address valid to end of write, with OE#
HIGH
Address setup time
Address hold from end of write
WRITE pulse width
WRITE pulse width, with OE# HIGH
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
Byte Enable to end of write
t
t
- 10
SYM
t
- 12
MIN
MAX
- 15
MIN
MAX
- 20
MIN
MAN
UNITS NOTES
MIN
MAX
RC
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
t
10
10
10
3
3
5
5
0
5
6
0
5
0
10
10
8
8
0
0
10
8
6
0
3
5
8
12
12
12
4
4
6
6
0
6
7
0
6
0
12
12
8
8
0
0
10
8
6
0
4
6
8
15
15
15
4
4
7
7
0
7
8
0
7
0
15
15
9
9
0
0
11
9
7
0
5
7
9
20
20
20
4
4
8
8
0
8
9
0
8
0
20
20
10
10
0
0
12
10
8
0
5
8
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 7
4, 6, 7
HZOE
t
ABE
t
LZBE
t
HZBE
t
PU
t
PD
t
t
4, 6
4, 7
4, 6, 7
4
4
WC
CW
t
AW
AS
AH
t
WP2
t
t
t
WP1
t
DS
t
DH
LZWE
HZWE
t
BW
4, 7
4, 6, 7
June 14, 1996
Rev. 6/96
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
