ADVANCE INFORMATION
GALVANTECH
, INC.
ASYNCHRONOUS
SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Fast access times: 10, 12, 15and 20ns
Fast OE# access times: 5, 6, 7 and 8ns
Single +3.3V +0.3V power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise immunity
Easy memory expansion with CE# and OE# options
Automatic CE# power down
High-performance, low-power consumption, CMOS
triple-poly, double-metal process
Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil
TSOP
GVT73128A16
REVOLUTIONARY PINOUT 128K X 16
128K x 16 SRAM
+3.3V SUPPLY, SINGLE CHIP ENABLE
REVOLUTIONARY PINOUT
GENERAL DESCRIPTION
The GVT73128A16 is organized as a 131,072 x 16
SRAM using a four-transistor memory cell with a high
performance, silicon gate, low-power CMOS process.
Galvantech SRAMs are fabricated using triple-layer
polysilicon, double-layer metal technology.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable (CE#), separate byte
enable controls (BLE# and BHE#) and output enable (OE#)
with this organization.
The device offers a low power standby mode when chip
is not selected. This allows system designers to meet low
standby power requirements.
OPTIONS
•
Timing
10ns access
12ns access
15ns access
20ns access
Packages
44-pin SOJ (400 mil)
44-pin TSOP (400 mil)
Power consumption
Standard
Low
Temperature
Commercial
Industrial
MARKING
-10
-12
-15
-20
PIN ASSIGNMENT
44-Pin SOJ
44-Pin TSOP
A4
A3
A2
A1
A0
CE#
DQ1
DQ2
DQ3
DQ4
VCC
VSS
DQ5
DQ6
DQ7
DQ8
WE#
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
•
J
TS
•
None
L
•
None
I
(
0°C
to
70°C)
(
-40°C
to
85°C)
A5
A6
A7
OE#
BHE#
BLE#
DQ16
DQ15
DQ14
DQ13
VSS
VCC
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699
Rev. 12/9 7
Galvantech, Inc. reserves the right to chang e
products or specifications without notice.
ADVANCE INFORMATION
GALVANTECH
,INC.
FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
GVT73128A16
REVOLUTIONARY PINOUT 128K X 16
BLE#
A0
DQ1
ROW DECODER
I/O CONTROL
ADDRESS BUFFER
MEMORY ARRAY
512 ROWS X 256 X 16
COLUMNS
DQ8
DQ9
DQ16
A16
COLUMN DECODER
POWER
DOWN
CE#
BHE#
WE#
OE#
December 11, 199 7
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/9 7
ADVANCE INFORMATION
GALVANTECH
,INC.
TRUTH TABLE
MODE
LOW BYTE READ (DQ1-DQ8)
HIGH BYTE READ (DQ9-DQ16)
WORD READ (DQ1-DQ16)
LOW BYTE WRITE (DQ1-DQ8)
HIGH BYTE WRITE (DQ9-DQ16)
WORD WRITE (DQ1-DQ16)
OUTPUT DISABLE
STANDBY
CE#
L
L
L
L
L
L
L
L
H
WE#
H
H
H
L
L
L
X
H
X
GVT73128A16
REVOLUTIONARY PINOUT 128K X 16
OE#
L
L
L
X
X
X
X
H
X
BLE#
L
H
L
L
H
L
H
X
X
BHE#
H
L
L
H
L
L
H
X
X
DQ1-
DQ8
Q
HIGH-Z
Q
D
HIGH-Z
D
HIGH-Z
HIGH-Z
HIGH-Z
DQ9-
DQ16
HIGH-Z
Q
Q
HIGH-Z
D
D
HIGH-Z
HIGH-Z
HIGH-Z
POWER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
STANDBY
PIN DESCRIPTIONS
SOJ & TSOP
Pin Numbers
5, 4, 3, 2, 1, 44, 43,
42, 27, 26, 25, 24,
22, 21, 20, 19, 18
17
6
SYMBOL
A0-A16
TYPE
Input
DESCRIPTION
Addresses Inputs: These inputs determine which cell is addressed.
WE #
CE#
Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW
for a WRITE cycle and HIGH for a READ cycle .
Chip Enable: This active LOW input is used to enable the device. When CE# is LOW, the
chip is selected. When CE# is HIGH, the chip is disabled and automatically goes into
standby power mode.
Byte Enable: These active LOW inputs allow individual bytes to be written or read. When
BLE# is LOW, the data is written to or read from the lower byte (DQ1-DQ8). When BHE# is
LOW, the data is written to or read from the higher byte (DQ9-DQ16).
Output Enable: This active LOW input enables the output drivers.
Input
39, 40
BLE#, BHE#
Input
41
7, 8, 9, 10, 13, 14,
15, 16, 29, 30, 31,
32, 35, 36, 37, 38
11, 33
12, 34
O E#
DQ1-DQ16
Input
Input/Output SRAM Data I/O: Data inputs and data outputs. Lower byte is DQ1-DQ8 and upper byte is
DQ9-DQ16.
Supply
Supply
Power Supply: 3.3V
+
0.3V
Ground
VCC
VSS
December 11, 199 7
3
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/9 7
ADVANCE INFORMATION
GALVANTECH
,INC.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V
V
IN
..........................................................-0.5V to VCC+1.0V
Storage Temperature (plastic) ..........................-55
o
C to +125
o
Junction Temperature .....................................................+125
o
Power Dissipation ...........................................................1.0W
Short Circuit Output Current .......................................50mA
GVT73128A16
REVOLUTIONARY PINOUT 128K X 16
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
0V < V
IN
< VCC
Output(s) disabled,
0V < V
OUT
< VCC
I
OH
= -4.0mA
I
OL
= 8.0mA
CONDITIONS
SYMBOL
V
IH
V
Il
IL
I
IL
O
V
OH
V
OL
VCC
MIN
2.2
-0.5
-5
-5
2.4
MAX
VCC+0.5
0.8
5
5
UNITS
V
V
uA
uA
V
NOTES
1, 2
1, 2
1
1
1
0.4
3.0
3.6
V
V
DESCRIPTION
Power Supply
Current: Operating
TTL Standby
CONDITIONS
Device selected; CE# < V
IL
; VCC =MAX;
f= f
MAX
; outputs open
CE# >V
IH
; VCC = MAX; f=f
MAX
CE1# >VCC -0.2; VCC = MAX;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0
SYM
Ic c
I
SB1
I
SB2
TYP
70
10
POWER
-10
190
180
35
30
3
0.3
-12
160
150
30
25
3
0.3
-15
130
120
25
20
3
0.3
-20
100
90
20
15
3
0.3
UNIT S
NOTES
mA
mA
3, 14
14
standard
low
standard
low
standard
low
CMOS Standby
0.02
mA
14
CAPACITANCE
DESCRIPTION
Input Capacitance
Input/Output Capacitance (DQ)
CONDITIONS
T
A
= 25
o
C; f = 1 MHz
VCC = 3.3V
SYMBOL
C
I
C
I/O
MAX
6
8
UNITS
pF
pF
NOTES
4
4
December 11, 199 7
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/9 7
ADVANCE INFORMATION
GALVANTECH
,INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 3.3V
+
0.3V)
DESCRIPTION
READ Cycle
READ cycle tim e
Address access time
Chip Enable access time
Output hold from address chang e
Chip Enable to output in Low- Z
Chip disable to output in High-Z
Output Enable access time
Output Enable to output in Low- Z
Output Enable to output in High-Z
Byte Enable access tim e
Byte Enable to output in Low-Z
Byte disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down tim e
WRITE Cycle
WRITE cycle tim e
Chip Enable to end of write
Address valid to end of write, with OE#
HIGH
Address setup time
Address hold from end of write
WRITE pulse width
WRITE pulse width, with OE# HIGH
Data setup tim e
Data hold tim e
Write disable to output in Low-Z
Write Enable to output in High-Z
Byte Enable to end of write
t
t
t
RC
t
A A
t
ACE
t
OH
t
LZC E
t
HZC E
t
AO E
t
LZOE
t
HZOE
t
ABE
t
LZBE
t
HZB E
t
PU
t
PD
GVT73128A16
REVOLUTIONARY PINOUT 128K X 16
- 10
SY M
MIN
MAX
- 12
MIN
MAX
MIN
- 15
MAX
MIN
- 20
MAN
UNIT S NOTES
10
10
10
3
3
5
5
0
5
6
0
5
0
10
10
8
8
0
0
10
8
5
0
3
5
8
12
12
12
4
4
6
6
0
6
7
0
6
0
12
12
8
8
0
0
10
8
6
0
4
6
8
15
15
15
4
4
7
7
0
7
8
0
7
0
15
15
9
9
0
0
11
9
7
0
5
7
9
20
20
20
4
4
8
8
0
8
9
0
8
0
20
20
10
10
0
0
12
10
8
0
5
8
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 7
4, 6, 7
4, 7
4, 6, 7
4
4
4, 6
4, 7
4, 6, 7
WC
t
CW
t
AW
t
A S
t
AH
t
WP2
t
WP1
t
DS
t
DH
t
LZWE
HZW E
t
BW
December 11, 199 7
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/9 7
