GALVANTECH
, INC.
ASYNCHRONOUS
SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Fast access times: 10, 12 and 15ns
Fast OE# access times: 5, 6and 7ns
Single +3.3V +0.3V power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise immunity
JEDEC standard for functionality and revolutionary pinout
Easy memory expansion with CE# and OE# options
Automatic CE# power down
High-performance, low-power consumption, CMOS
double-poly, double-metal process
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
512K x 8 SRAM
+3.3V SUPPLY
REVOLUTIONARY PINOUT
GENERAL DESCRIPTIO N
The GVT73512A8 is organized as a 524,288 x 8 SRAM
using a four-transistor memory cell with a high performance,
silicon gate, low-power CMOS process. Galvantech SRAMs
are fabricated using double-layer polysilicon, double-layer
metal technology.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable (CE#) and output
enable (OE#) with this organization.
Writing to these devices is accomplished when write
enable (WE#) and chip enable (CE#) inputs are both LOW.
Reading is accomplished when (CE#) and (OE#) go LOW
with (WE#) remaining HIGH. The device offers a low power
standby mode when chip is not selected. This allows system
designers to meet low standby power requirements.
OPTIONS
•
Timing
10ns access
12ns access
15ns access
Packages
36-pin SOJ (400 mil)
Power consumption
Standard
Low
Temperature
Commercial
Industrial
MARKING
-10
-12
-15
•
J
A0
A1
A2
A3
A4
CE#
DQ1
DQ2
VCC
VSS
DQ3
DQ4
WE#
A5
A6
A7
A8
A9
PIN ASSIGNMENT
36-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
•
None
L
•
None
I
(
0°C
to
70°C)
(
-40°C
to
85°C)
NC
A18
A17
A16
A15
OE#
DQ8
DQ7
VSS
VCC
DQ6
DQ5
A14
A13
A12
A11
A10
NC
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com
Rev. 1/99
Galvantech, Inc. reserves the right to chang
e
products or specifications without notice
.
GALVANTECH
,
FUNCTIONAL BLOCK DIAGRAM
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
VCC
VSS
A0
DQ1
ROW DECODER
ADDRESS BUFFER
MEMORY ARRAY
1024 ROWS X 512 X 8
COLUMNS
I/O CONTROL
DQ8
CE#
WE#
OE#
A18
COLUMN DECODER
POWER
DOWN
TRUTH TABLE
MODE
READ
WRITE
OUTPUT DISABLE
STANDBY
CE#
L
L
L
H
WE#
H
L
H
X
OE#
L
X
H
X
DQ
Q
D
HIGH-Z
HIGH-Z
POWER
ACTIVE
ACTIVE
ACTIVE
STANDBY
PIN DESCRIPTION S
SOJ Pin
Numbers
1, 2, 3, 4, 5, 14, 15,
16, 17, 18, 20, 21,
22, 23, 24, 32, 33,
34, 35
13
6
SYMBOL
A0-A18
TYPE
Input
DESCRIPTION
Addresses Inputs: These inputs determine which cell is addressed .
WE#
CE#
Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW
for a WRITE cycle and HIGH for a READ cycle .
Chip Enable: This active LOW input is used to enable the device. When CE# is LOW, the
chip is selected. When CE# is HIGH, the chip is disabled and automatically goes into
standby power mode .
Output Enable: This active LOW input enables the output drivers .
Input
31
7, 8,11, 12,
25, 26, 29, 3 0
9, 27
10, 28
OE#
DQ1-DQ8
VCC
VSS
Input
Input/Outpu t SRAM Data I/O: Data inputs and data output s
Supply
Supply
Power Supply:3.3V
+
0.3V
Ground
January 20, 199 9
2
Galvantech, Inc. reserves the right to change products or specifications without notice
.
Rev. 1/99
GALVANTECH
,
ABSOLUTE MAXIMUM RATINGS *
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V
V
IN
..........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ..........................-55
o
C to +125
o
Junction Temperature .....................................................+125
o
Power Dissipation ...........................................................1.2W
Short Circuit Output Current .......................................50mA
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability
.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITION S
(All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) voltag e
Input Low (Logic 0) Voltag e
Input Leakage Curren t
Output Leakage Curren t
Output High Voltag e
Output Low Voltag e
Supply Voltag e
0V < V
IN
< VCC
Output(s) disabled,
0V < V
OUT
< VCC
I
OH
= -4.0mA
I
OL
= 8.0mA
CONDITIONS
SYMBOL
V
IH
V
Il
IL
I
IL
O
V
OH
V
OL
VCC
MIN
2.2
-0.5
-5
-5
2.4
MAX
VCC+0.5
0.8
5
5
UNITS
V
V
uA
uA
V
NOTES
1, 2
1, 2
1
1
1
0.4
3.0
3.6
V
V
DESCRIPTION
Power Supply
Current: Operatin g
TTL Standb y
CMOS Standb y
CONDITIONS
Device selected; CE# < V
IL
; VCC =MAX;
f=f
MAX
; outputs ope n
CE# >V
IH
; VCC = MAX; f=f
MAX
CE1# >VCC -0.2; VCC = MAX ;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0
SYM
Icc
I
SB1
I
SB2
TYP
90
30
0.1
POWER
-10
240
240
70
70
10
3.0
-12
210
210
60
60
10
3.0
-15
175
175
50
50
10
3.0
UNITS
NOTES
mA
mA
mA
3, 14
14
14
standard
low
standard
low
standard
low
CAPACITANCE
DESCRIPTION
Input Capacitanc e
Input/Output Capacitance (DQ )
CONDITIONS
T
A
= 25
o
C; f = 1 MH z
VCC = 3.3V
SYMBOL
C
I
C
I/O
MAX
6
8
UNITS
pF
pF
NOTES
4
4
January 20, 199 9
3
Galvantech, Inc. reserves the right to change products or specifications without notice
.
Rev. 1/99
GALVANTECH
,
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 3.3V
+
0.3V)
DESCRIPTION
READ Cycle
READ cycle tim e
Address access tim e
Chip Enable access tim e
Output hold from address chang e
Chip Enable to output in Low- Z
Chip disable to output in High- Z
Output Enable access tim e
Output Enable to output in Low- Z
Output Enable to output in High- Z
Chip Enable to power-up tim e
Chip disable to power-down tim e
WRITE Cycl
e
WRITE cycle tim e
Chip Enable to end of writ e
Address valid to end of write, with OE#
HIGH
Address setup tim e
Address hold from end of writ e
WRITE pulse widt h
WRITE pulse width, with OE# HIG H
Data setup tim e
Data hold tim e
Write disable to output in Low- Z
Write Enable to output in High- Z
t
t
t
t
t
t
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
- 10
SYM
MIN
MAX
- 12
MIN
MAX
- 15
MIN
MAX
UNITS NOTES
RC
AA
10
10
10
3
3
5
5
0
5
0
10
10
8
8
0
0
10
8
5
0
3
6
12
12
12
3
3
6
6
0
6
0
12
12
8
8
0
0
10
8
6
0
4
6
15
15
15
3
3
7
7
0
7
0
15
15
9
9
0
0
11
9
7
0
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 7
4, 6, 7
4, 6
4
4
4, 7
4, 6, 7
t
t
ACE
t
OH
LZCE
t
t
HZCE
AOE
LZOE
t
t
HZOE
PU
PD
WC
CW
AW
t
t
AS
t
AH
t
WP2
t
WP1
t
DS
t
DH
t
LZWE
t
HZWE
January 20, 199 9
4
Galvantech, Inc. reserves the right to change products or specifications without notice
.
Rev. 1/99
GALVANTECH
,
AC TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
0V to 3.0V
1.5ns
1.5V
1.5V
See Figures 1 and 2
GVT73512A8
REVOLUTIONARY PINOUT 512K X 8
OUTPUT LOADS
DQ
Z
0
= 50Ω
50Ω
Vt = 1.5V
Fig. 1 OUTPUT LOAD EQUIVALENT
3.3v
317Ω
DQ
351Ω
5 pF
30 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1.
2.
3.
4.
5.
6.
7.
All voltages referenced to VSS (GND).
Overshoot:
Undershoot:
V
IH
≤
+6.0V for t
≤
t
RC /2.
V
IL
≤
-2.0V for t
≤
t
RC /2
8.
9.
WE# is HIGH for READ cycle.
Device is continuously selected. Chip enable and output enables
are held in their active state.
I
cc
is given with no output current. I
cc
increases with greater
output loading and faster cycle times.
This parameter is sampled.
Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
Output loading is specified with C
L
=5pF as in Fig. 2. Transition
is measured +500mV from steady state voltage.
At any given temperature and voltage condition,
t
HZCE is less
than
t
LZCE and
t
HZWE is less than
t
LZWE.
10. Address valid prior to, or coincident with, latest occurring chip
enable.
11.
t
RC
= Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a
WRITE cycle.
13. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1.
14. Typical values are measured at 3.3V, 25
o
C and 20ns cycle time.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only )
DESCRIPTION
Vcc for Retention Dat a
Data Retention Curren t
CE# >VCC -0.2;
all other inputs < VSS +0.2
or >VCC -0.2;
all inputs static; f= 0
Vcc = 2V
Vcc = 3V
CONDITIONS
SYMBOL
MIN
2
TYP
MAX
UNITS
V
NOTES
V
DR
I
CCDR
I
CCDR
t
CDR
t
R
0.2
0.3
0
1.6
2.4
mA
mA
ns
ns
13
13
4
4, 11
Chip Deselect to
Data Retention Tim e
Operation Recovery Tim e
t
RC
January 20, 199 9
5
Galvantech, Inc. reserves the right to change products or specifications without notice
.
Rev. 1/99
模拟与混合信号
