ADVANCE INFORMATION
GALVANTECH
, INC.
SYNCHRONOUS
DUAL-PORT
BURST SRAM
FEATURES
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True Dual-Ported memory cells which allow simultaneous
access of the same memory location.
Fast access times: 4.5ns, 5.0ns, and 6.0ns
Fast clock speed: 125, 100, 83, and 66MHz
Fast OE# access times: 4.5ns, 5.0ns, and 6.0ns
Address, data and control registers
5.0V + 0.5V power supply
Address burst counters enable and reset capabilities
Dual Chip Enables for easy depth expansion
Fully synchronous interface on both ports
3 operating modes: Flow-Through, Pipelined, and Burst
Dual chip enables for depth expansion
BYTE ENABLE controls for x16 and x18 devices
Internally self-timed WRITE CYCLE
Automatic power-down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP package
Clock Cycle Timing
8ns (125MHz)
10ns (100MHz)
12ns (83MHz)
15ns (67MHz)
16K x 16
16K x 18
32K x 16
32K x 18
64K x 16
64K x 18
32K x 8
32K x 9
64K x 8
64K x 9
128K x 8
128K x 9
GVT7464/32/16C16/18
GVT74128/64/32C8/9
64K/32K/16K x 16/18
128K/64K/32K x 8/9
+5V SUPPLY, BURST COUNTER
GNERAL DESCRIPTION
The
GVT7416C16/18,
GVT7432C16/18,
and
GVT7464C16/18 are high speed synchronous 16K, 32K and
64K x 16/18 dual-port static RAMs; the GVT7432C8/9,
GVT7464C8/9, and GVT74128C8/9 are high speed
synchronous 32K, 64K, and 128K x 8/9 dual-port static
RAMs. Dual-port memory cells are provided, permitting
independent, simultaneous access for reads and writes to any
address location in these devices. Registers on address, data,
and control inputs allow for minimal set-up and hold times.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK).
Each port contains a burst counter on the input address
register for internal burst operation. The address burst counter
can be incremented, suspended or reset to zero, depending
upon the CNTEN# and CNTRST# pins.
In the pipelined mode, output data will be valid after one
cycle delay. Flow-through mode can be used to bypass the
pipelined output register to eliminate one cycle latency.
Pipelined or flow-through mode is selected by the FT# pin.
The port of the device is activated by asserting LOW on
CE0# and HIGH on CE1 at the rising edge of CLK. By
asserting HIGH on CE0# or LOW on CE1 at the rising edge
of CLK signal will power down the internal circuitry to
reduce the static power consumption. The use of multiple
Chip Enables allows easier banking of multiple chips for
depth expansion configurations.
Counter enable inputs are provided to utilize the internal
address generated by the internal counter for fast memory
applications. A port’s address burst conter is loaded with the
port’s address strobe (ADS#). When the port’s count enable
(CNTEN#) is asserted, the address burst counter will
increment on each LOW-to-HIGH transition of the port’s
clock signal. This will read/write one word from/into each
successive address location until CNTEN is deasserted. The
address burst counter can address the entire memory array and
will loop back to the start. Counter reset (CNTRST#) is used
to reset the address burst counter.
MARKING
-8
-10
-12
-15
GVT7416C16
GVT7416C18
GVT7432C16
GVT7432C18
GVT7464C16
GVT7464C18
GVT7432C8
GVT7432C9
GVT7464C8
GVT7464C9
GVT74128C8
GVT74128C9
T
Configurations
Package Versions
100-pin TQFP
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com
Rev. 8/99
Galvantech, Inc. reserves the right to change
products or specifications without notice.
ADVANCE INFORMATION
GALVANTECH
, INC.
WEL#
UBL#
CE0L#
1
GVT7464/32/16C16/18
GVT74128/64/32C8/9
16K/32K/64K X 16/18 FUNCTIONAL BLOCK DIAGRAM
WER#
UBR#
CE0R#
1
0
0/1
0
0/1
CE1L
LBL#
OEL#
CE1R
LBR#
OER#
FTL#
[3]
DQ15/17L-
0/1
1
0
1
0
0
1
0
1
0/1
FTR#
DQ15/17R-
DQ8/9R
[3]
DQ7/8R-
DQ0R
[2]
8/9
8/9
DQ8/9L
[2]
DQ7/8L-
8/9
I/O
Control
I/O
Control
8/9
DQ0L
A13/14/15L-
[1]
A0L
CLKL
ADSL#
CNTENL#
CNTRSTL#
14/15/16
14/15/16
Counter/Address
Registers/
Decoder
TRUE DUAL-PORT
MEMORY ARRAY
Counter/Address
Registers/
Decoder
A13/14/15R-
A0R
[1]
CLKR
ADSR#
CNTENR#
CNTRSTR#
Notes:
1. A13-A0 for 16K devices; A14-A0 for 32K devices; A15-A0 for 64K devices.
2. DQ7-DQ0 for x16 devices; DQ8-DQ0 for x18 devices.
3. DQ15-DQ8 for x16 devices; DQ17-DQ9 for x18 devices.
32K/64K/128K X 8/9 FUNCTIONAL BLOCK DIAGRAM
WEL#
OEL#
CE0L#
CE1L
1
0
0/1
1
0
0/1
WER#
OER#
CE0R#
CE1R
FTL#
0/1
1
0
0
1
0/1
FTR#
[2]
DQ7/8L-
8/9
DQ0L
A14/15/16L-
[1]
A0L
CLKL
ADSL#
CNTENL#
CNTRSTL#
15/16/17
I/O
Control
I/O
Control
8/9
DQ7/8R-
DQ0R
[2]
15/16/17
Counter/Address
Registers/
Decoder
TRUE DUAL-PORT
MEMORY ARRAY
Counter/Address
Registers/
Decoder
A14/15/16R-
A0R
[1]
CLKR
ADSR#
CNTENR#
CNTRSTR#
Notes:
1. A14-A0 for 32K devices; A15-A0 for 64K devices; A16-A0 for 128K devices.
2. DQ7-DQ0 for x8 devices; DQ8-DQ0 for x9 devices.
August 9, 1999
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
ADVANCE INFORMATION
GALVANTECH
, INC.
16K/32K/64K X 16,
100-PIN TQFP (Top View)
GVT7464/32/16C16/18
GVT74128/64/32C8/9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
(Note 2) A14L
(Note 1) A15L
NC
NC
LBL#
UBL#
CE0L#
CE1L
CNTRSTL#
VCC
WEL#
OEL#
FTL#
VSS
DQ15L
DQ14L
DQ13L
DQ12L
DQ11L
DQ10L
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
CNTENL#
CLKL
ADSL#
VSS
ADSR#
CLKR
CNTENR#
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
GVT7464V16 (64k X 16)
GVT7432V16 (32k X 16)
GVT7416V16 (16k X 16)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A9R
A10R
A11R
A12R
A13R
A14R (Note 2)
A15R (Note 1)
NC
NC
LBR#
UBR#
CE0R#
CE1R
CNTRSTR#
VSS
WER#
OER#
FTR#
VSS
DQ15R
DQ14R
DQ13R
DQ12R
DQ11R
DQ10R
Notes:
1. These pins are NC for 32K x 16 and 16K x 16 devices.
2. These pins are NC for 16K x 16 devices.
August 9, 1999
Rev. 8/99
DQ9L
DQ8L
VCC
DQ7L
DQ6L
DQ5L
DQ4L
DQ3L
DQ2L
VSS
DQ1L
DQ0L
VSS
DQ0R
DQ1R
DQ2R
DQ3R
DQ4R
DQ5R
DQ6R
VCC
DQ7R
DQ8R
DQ9R
NC
3
Galvantech, Inc. reserves the right to change products or specifications without notice.
ADVANCE INFORMATION
GALVANTECH
, INC.
16K/32K/64K X 18,
100-PIN TQFP (Top View)
GVT7464/32/16C16/18
GVT74128/64/32C8/9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
(Note 2) A14L
(Note 1) A15L
LBL#
UBL#
CE0L#
CE1L
CNTRSTL#
WEL#
OEL#
VCC
FTL#
DQ17L
DQ16L
VSS
DQ15L
DQ14L
DQ13L
DQ12L
DQ11L
DQ10L
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
CNTENL#
CLKL
ADSL#
VSS
VSS
ADSR#
CLKR
CNTENR#
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
GVT7464V18 (64k X 18)
GVT7432V18 (32k X 18)
GVT7416V18 (16k X 18)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A8R
A9R
A10R
A11R
A12R
A13R
A14R (Note 2)
A15R (Note 1)
LBR#
UBR#
CE0R#
CE1R
CNTRSTR#
WER#
VSS
OER#
FTR#
DQ17R
VSS
DQ16R
DQ15R
DQ14R
DQ13R
DQ12R
DQ11R
Notes:
1. These pins are NC for 32K x 18 and 16K x 18 devices.
2. These pins are NC for 16K x 18 devices.
August 9, 1999
Rev. 8/99
DQ9L
DQ8L
VCC
DQ7L
DQ6L
DQ5L
DQ4L
DQ3L
DQ2L
VSS
DQ1L
DQ0L
VSS
DQ0R
DQ1R
DQ2R
DQ3R
DQ4R
DQ5R
DQ6R
VCC
DQ7R
DQ8R
DQ9R
DQ10R
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
ADVANCE INFORMATION
GALVANTECH
, INC.
32K/64K/128K X 8,
100-PIN TQFP (Top View)
GVT7464/32/16C16/18
GVT74128/64/32C8/9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
(Note 2) A15L
(Note 1) A16L
VCC
NC
NC
NC
NC
CE0L#
CE1L
CNTRSTL#
WEL#
OEL#
FTL#
NC
NC
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
CNTENL#
CLKL
ADSL#
VSS
ADSR#
CLKR
CNTENR#
A0R
A1R
A2R
A3R
A4R
A5R
A6R
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
GVT74128V8 (128k X 8)
GVT7464V8 (64k X 8)
GVT7432V8 (32k X 8)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R (Note 2)
A16R (Note 1)
VSS
NC
NC
NC
NC
CE0R#
CE1R
CNTRSTR#
WER#
OER#
FTR#
VSS
NC
Notes:
1. These pins are NC for 64K x 8 and 32K x 8 devices.
2. These pins are NC for 32K x 8 devices.
August 9, 1999
Rev. 8/99
VSS
NC
DQ7L
DQ6L
DQ5L
DQ4L
DQ3L
DQ2L
VSS
DQ1L
DQ0L
VCC
VSS
DQ0R
DQ1R
DQ2R
VCC
DQ3R
DQ4R
DQ5R
DQ6R
DQ7R
NC
NC
NC
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
