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512Mb DDR SDRAM

H5DU5182EFR

H5DU5162EFR

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.0 / Nov. 2009

1H5DU5182EFR

H5DU5162EFR

Revision History

Revision No.

0.1

1.0

History

Preliminary

Release

Draft Date

Sep. 2009

Nov. 2009

Remark

Rev. 1.0 / Nov. 2009

1H5DU5182EFR

H5DU5162EFR

DESCRIPTION

The H5DU5182EFR and H5DU5162EFR are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ide-

ally suited for the main memory applications which requires large memory density and high bandwidth.

This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,

Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible

with SSTL_2.

FEATURES

•

, V

DDQ

= 2.5V +/- 0.2V

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock inputs (CK, /CK) operation

Double data rate interface

Source synchronous - data transaction aligned to

bidirectional data strobe (DQS)

x16 device has two bytewide data strobes (UDQS,

LDQS) per each x8 I/O

Data outputs on DQS edges when read (edged DQ)

Data inputs on DQS centers when write (centered

DQ)

On chip DLL align DQ and DQS transition with CK

transition

DM mask write data-in at the both rising and falling

edges of the data strobe

•

All addresses and control inputs except data, data

strobes and data masks latched on the rising edges

of the clock

Programmable CAS latency 2/2.5 (DDR200, 266,

333), 3 (DDR400) and 4 (DDR500) supported

Programmable burst length 2/4/8 with both sequen-

tial and interleave mode

Internal four bank operations with single pulsed

/RAS

Auto refresh and self refresh supported

RAS

lock out function supported

8192

refresh cycles/64ms

60 Ball FBGA Package Type

This product is in compliance with the directive per-

taining of RoHS.

•

ORDERING INFORMATION

Part No.

H5DU5182EFR-XXC

H5DU5162EFR-XXC

Configuration

64Mx8

32Mx16

Package

60 Ball

FBGA

OPERATING FREQUENCY

Grade

- FA

- E3

Clock Rate

250MHz@CL4

200MHz@CL3, 166MHz@CL2.5,

133MHz@CL2

Remark

(CL-tRCD-tRP)

DDR500 (4-4-4)

DDR400 (3-3-3),

DDR333 (2.5-3-3),

DDR266A (2-3-3),

DDR266B (2.5-3-3)

DDR333 (2.5-3-3),

DDR266A (2-3-3),

DDR266B (2.5-3-3)

DDR266A (2-3-3),

DDR266B (2.5-3-3)

DDR200 (2-2-2)

*X means speed grade

*ROHS (Restriction Of Hazardous Substance)

- J3

166MHz@CL2.5, 133MHz@CL2

- K2

- K3

- L2

133MHz@CL2, 133MHz@CL2.5

133MHz@CL2.5, 100MHz@CL2

100MHz@CL2

* Higher speed part is compatible with the lower speed part.

Rev. 1.0 / Nov. 2009

1H5DU5182EFR

H5DU5162EFR

BALL CONFIGURATION

(X8)

(X16)

VSSQ

DQ7

VSS

VDD

DQ0

VDDQ

VSSQ

DQ15

VSS

VDD

DQ0

VDDQ

DQ6

DQ1

VSSQ

DQ14

VDDQ

DQ13

DQ2

VSSQ

DQ1

VSSQ

DQ5

DQ2

VDDQ

DQ12

VSSQ

DQ11

DQ4

VDDQ

DQ3

VDDQ

DQ4

DQ3

VSSQ

DQ10

VDDQ

DQ9

DQ6

VSSQ

DQ5

VSSQ

DQS

VDDQ

DQ8

VSSQ

UDQS

LDQS

VDDQ

DQ7

VREF

VSS

VDD

VREF

VSS

UDM

LDM

VDD

CAS

A12

CKE

RAS

A12

CKE

RAS

A11

BA1

BA0

A11

BA1

BA0

A10/AP

VSS

VDD

VSS

VDD

x8 Device Ball Pattern

x16 Device Ball Pattern

: B all E xisting

: D epopu lated B all

[ F or R eferen ce O nly ]

Top V iew (See the b alls th rough the P ackage)

12 .0m m

1.0m m

8.0m m

0.8m m

B G A P ackage B all P attern

Top View

ROW AND COLUMN ADDRESS TABLE

ITEMS

Organization

Row Address

Column Address

Bank Address

Auto Precharge Flag

Refresh

64Mx8

16M x 8 x 4banks

A0 - A12

A0-A9, A11

BA0, BA1

A10

32Mx16

8M x 16 x 4banks

A0 - A12

A0-A9

BA0, BA1

A10

Rev. 1.0 / Nov. 2009

1H5DU5182EFR

H5DU5162EFR

PIN DESCRIPTION

TYPE

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input

signals are sampled on the crossing of the positive edge of CK and negative

edge of /CK. Output (read) data is referenced to the crossings of CK and /CK

(both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock sig-

nals, and device input buffers and output drivers. Taking CKE LOW provides

PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or

ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for

POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchro-

nous for SELF REFRESH exit, and for output disable. CKE must be maintained

high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK

and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVC-

MOS LOW level after VDD is applied.

Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM.

All commands are masked when CS is registered high. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the

command code.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read,

Write or PRECHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the col-

umn address and AUTO PRECHARGE bit for READ/WRITE commands, to select

one location out of the memory array in the respective bank. A10 is sampled

during a Precharge command to determine whether the PRECHARGE applies to

one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be pre-

charged, the bank is selected by BA0, BA1. The address inputs also provide the

op code during a MODE REGISTER SET command. BA0 and BA1 define which

mode register is loaded during the MODE REGISTER SET command (MRS or

EMRS).

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command

being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is

masked when DM is sampled HIGH along with that input data during a WRITE

access. DM is sampled on both edges of DQS. Although DM pins are input only,

the DM loading matches the DQ and DQS loading. For the x16, LDM corre-

sponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15.

Data Strobe: Output with read data, input with write data. Edge aligned with

read data, centered in write data. Used to capture write data. For the x16,

LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on

DQ8-Q15.

Data input / output pin: Data bus

Power supply for internal circuits and input buffers.

Power supply for output buffers for noise immunity.

Reference voltage for inputs for SSTL interface.

No connection.

CK, /CK

Input

CKE

Input

/CS

Input

BA0, BA1

Input

A0 ~ A12

Input

/RAS, /CAS, /

Input

(LDM,UDM)

Input

DQS

(LDQS,UDQS)

VDD/VSS

VDDQ/VSSQ

VREF

Rev. 1.0 / Nov. 2009

I/O

Supply

参数对比

与H5DU5182EFR-J3C相近的元器件有：H5DU5162EFR、H5DU5162EFR-J3C、H5DU5162EFR-K3C、H5DU5162EFR-FAC、H5DU5162EFR-L2C、H5DU5182EFR-E3C、H5DU5182EFR、H5DU5182EFR-K2C、H5DU5182EFR-K3C。描述及对比如下：

型号	H5DU5182EFR-J3C	H5DU5162EFR	H5DU5162EFR-J3C	H5DU5162EFR-K3C	H5DU5162EFR-FAC	H5DU5162EFR-L2C	H5DU5182EFR-E3C	H5DU5182EFR	H5DU5182EFR-K2C	H5DU5182EFR-K3C
描述	512Mb DDR SDRAM	512Mb DDR SDRAM	512Mb DDR SDRAM	512Mb DDR SDRAM	512Mb DDR SDRAM	512Mb DDR SDRAM	512Mb DDR SDRAM	512Mb DDR SDRAM	512Mb DDR SDRAM	512Mb DDR SDRAM
是否Rohs认证	符合	-	符合	符合	符合	符合	符合	-	符合	符合
厂商名称	SK Hynix(海力士)	-	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	-	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	BGA	-	BGA	BGA	BGA	BGA	BGA	-	BGA	BGA
包装说明	VBGA, BGA60,9X12,40/32	-	VBGA, BGA60,9X12,40/32	VBGA, BGA60,9X12,40/32	VBGA, BGA60,9X12,40/32	VBGA, BGA60,9X12,40/32	VBGA, BGA60,9X12,40/32	-	VBGA, BGA60,9X12,40/32	VBGA, BGA60,9X12,40/32
针数	60	-	60	60	60	60	60	-	60	60
Reach Compliance Code	unknow	-	unknow	unknow	unknow	unknow	unknow	-	unknow	unknow
ECCN代码	EAR99	-	EAR99	EAR99	EAR99	EAR99	EAR99	-	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	0.7 ns	-	0.7 ns	0.75 ns	0.65 ns	0.75 ns	0.7 ns	-	0.75 ns	0.75 ns
其他特性	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	166 MHz	-	166 MHz	133 MHz	250 MHz	100 MHz	200 MHz	-	133 MHz	133 MHz
I/O 类型	COMMON	-	COMMON	COMMON	COMMON	COMMON	COMMON	-	COMMON	COMMON
交错的突发长度	2,4,8	-	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	-	2,4,8	2,4,8
JESD-30 代码	R-PBGA-B60	-	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	-	R-PBGA-B60	R-PBGA-B60
JESD-609代码	e1	-	e1	e1	e1	e1	e1	-	e1	e1
长度	12 mm	-	12 mm	12 mm	12 mm	12 mm	12 mm	-	12 mm	12 mm
内存密度	536870912 bi	-	536870912 bi	536870912 bi	536870912 bi	536870912 bi	536870912 bi	-	536870912 bi	536870912 bi
内存集成电路类型	DDR DRAM	-	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	-	DDR DRAM	DDR DRAM
内存宽度	8	-	16	16	16	16	8	-	8	8
功能数量	1	-	1	1	1	1	1	-	1	1
端口数量	1	-	1	1	1	1	1	-	1	1
端子数量	60	-	60	60	60	60	60	-	60	60
字数	67108864 words	-	33554432 words	33554432 words	33554432 words	33554432 words	67108864 words	-	67108864 words	67108864 words
字数代码	64000000	-	32000000	32000000	32000000	32000000	64000000	-	64000000	64000000
工作模式	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	-	70 °C	70 °C	70 °C	70 °C	70 °C	-	70 °C	70 °C
组织	64MX8	-	32MX16	32MX16	32MX16	32MX16	64MX8	-	64MX8	64MX8
输出特性	3-STATE	-	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	-	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	VBGA	-	VBGA	VBGA	VBGA	VBGA	VBGA	-	VBGA	VBGA
封装等效代码	BGA60,9X12,40/32	-	BGA60,9X12,40/32	BGA60,9X12,40/32	BGA60,9X12,40/32	BGA60,9X12,40/32	BGA60,9X12,40/32	-	BGA60,9X12,40/32	BGA60,9X12,40/32
封装形状	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE	-	GRID ARRAY, VERY THIN PROFILE	GRID ARRAY, VERY THIN PROFILE	GRID ARRAY, VERY THIN PROFILE	GRID ARRAY, VERY THIN PROFILE	GRID ARRAY, VERY THIN PROFILE	-	GRID ARRAY, VERY THIN PROFILE	GRID ARRAY, VERY THIN PROFILE
峰值回流温度（摄氏度）	260	-	260	260	260	260	260	-	260	260
电源	2.5 V	-	2.5 V	2.5 V	2.5 V	2.5 V	2.6 V	-	2.5 V	2.5 V
认证状态	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
刷新周期	8192	-	8192	8192	8192	8192	8192	-	8192	8192
座面最大高度	1 mm	-	1 mm	1 mm	1 mm	1 mm	1 mm	-	1 mm	1 mm
自我刷新	YES	-	YES	YES	YES	YES	YES	-	YES	YES
连续突发长度	2,4,8	-	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	-	2,4,8	2,4,8
最大待机电流	0.005 A	-	0.005 A	0.005 A	0.005 A	-	0.005 A	-	0.005 A	0.005 A
最大压摆率	0.24 mA	-	0.24 mA	0.24 mA	0.31 mA	-	0.26 mA	-	0.24 mA	0.24 mA
最大供电电压 (Vsup)	2.7 V	-	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	-	2.7 V	2.7 V
最小供电电压 (Vsup)	2.3 V	-	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	-	2.3 V	2.3 V
标称供电电压 (Vsup)	2.5 V	-	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	-	2.5 V	2.5 V
表面贴装	YES	-	YES	YES	YES	YES	YES	-	YES	YES
技术	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS
温度等级	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	-	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	-	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
端子形式	BALL	-	BALL	BALL	BALL	BALL	BALL	-	BALL	BALL
端子节距	1 mm	-	1 mm	1 mm	1 mm	1 mm	1 mm	-	1 mm	1 mm
端子位置	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	20	-	20	20	20	20	20	-	20	20
宽度	8 mm	-	8 mm	8 mm	8 mm	8 mm	8 mm	-	8 mm	8 mm