128Mbit MOBILE DDR SDRAM based on 1M x 4Bank x32 I/O
Specification of
128M (4Mx32bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of 1,048,576 x32
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Jun. 2008
1
Mobile DDR SDRAM 128Mbit (4M x 32bit)
H5MS1222EFP Series
Document Title
128MBit (4Bank x 1M x 32bits) MOBILE DDR SDRAM
Revision History
Revision No.
0.1
0.2
0.3
0.4
1.0
- Initial Draft
- Define
IDD specification
- Correct
tREFi specification
- Modify
IDD values
-. Modify
IDD Values(p22,p23) , AC Characteristics(p.24)
History
Draft Date
Sep. 2007
Feb. 2008
May. 2008
Jun. 2008
Jun. 2008
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Rev 1.0 / Jun. 2008
2
Mobile DDR SDRAM 128Mbit (4M x 32bit)
H5MS1222EFP Series
FEATURES SUMMARY
●
Mobile DDR SDRAM
- Double data rate architecture: two data transfer per
clock cycle
●
Mobile DDR SDRAM INTERFACE
- x32 bus width: HY5MS5B2ALFP
- Multiplexed Address (Row address and Column ad-
dress)
●
BURST LENGTH
●
SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V
●
MEMORY CELL ARRAY
- 128Mbit (x32 device) = 1M x 4Bank x 32 I/O
●
DATA STROBE
- x32 device: DQS0 ~ DQS3
- Bidirectional, data strobe (DQS) is transmitted and re-
ceived with data, to be used in capturing data at the
receiver
- Data and data mask referenced to both edges of DQS
●
LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- DPD (Deep Power Down): DPD is an optional feature,
so please contact Hynix office for the DPD feature
●
INPUT CLOCK
- Differential clock inputs (CK, CK)
●
Data MASK
- DM0 ~ DM3: Input mask signals for write data
- DM masks write data-in at the both rising and
falling edges of the data strobe
●
PACKAGE
- HY5MS5B2ALFP: 90 Ball Lead free FBGA
●
CLOCK STOP MODE
- Clock stop mode is a feature supported by Mobile DDR
SDRAM.
- Keep to the JEDEC Standard regulation
●
INITIALIZING THE MOBILE DDR SDRAM
- Occurring at device power up or interruption of device
power
- Programmable burst length 2 / 4 / 8 with both sequen-
tial and interleave mode
●
AUTO PRECHARGE
- Option for each burst access
●
AUTO REFRESH AND SELF REFRESH MODE
●
CAS LATENCY
- Programmable CAS latency 2 or 3 supported
●
MODE RERISTER SET, EXTENDED MODE REGIS-
TER SET and STATUS REGISTER READ
- Keep to the JEDEC Standard regulation
(Low Power DDR SDRAM)
Rev 1.0 / Jun. 2008
3
Mobile DDR SDRAM 128Mbit (4M x 32bit)
H5MS1222EFP Series
DESCRIPTION
The Hynix H5MS1222EFP Series is 134,217,728-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile
DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones
with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 1,048,576
x32.
The HYNIX H5MS1222EFP series uses a double-data-rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2
n
prefetch architecture with an interface designed to transfer two data per clock
cycle at the I/O pins.
The Hynix H5MS1222EFP Series offers fully synchronous operations referenced to both rising and falling edges of the
clock. While all address and control inputs are latched on the rising edges of the CK (Mobile DDR SDRAM operates
from a differential clock
: the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK
),
data, data strobe and data mask inputs are sampled on both rising and falling edges of it (
Input data is registered on
both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK
). The data
paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. All input voltage levels are compatible
with LVCMOS.
Read and write accesses to the Low Power DDR SDRAM (Mobile DDR SDRAM) are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with
the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits reg-
istered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the bank and the starting column location
for the burst access.
The Low Power DDR SDRAM (Mobile DDR SDRAM) provides for programmable read or write bursts of 2, 4 or 8 loca-
tions. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end
of the burst access.
As with standard SDRAM, the pipelined and multibank architecture of Low Power DDR SDRAM (Mobile DDR SDRAM)
allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation
times.
The Low Power DDR SDRAM (Mobile DDR SDRAM) also provides for special programmable Self Refresh options which
are Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array) and Temperature Compensated Self Refresh.
A burst of Read or Write cycles in progress can be interrupted and replaced by a new burst Read or Write command on
any cycle (this pipelined design is not restricted by a 2N rule). Only Read bursts in progress with auto precharge disa-
bled can be terminated by a burst terminate command. Burst Terminate command is undefined and should not be
used for Read with Autoprecharge enabled and for Write bursts.
Rev 1.0 / Jun. 2008
4
Mobile DDR SDRAM 128Mbit (4M x 32bit)
H5MS1222EFP Series
The Hynix H5MS1222EFP series has the special Low Power function of Auto TCSR (Temperature Compensated Self
Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implemented, it enables
to automatically adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is an additional operating mode for Low Power DDR SDRAM (Mobile DDR SDRAM). This mode
can achieve maximum power reduction by removing power to the memory array within Low Power DDR SDRAM
(Mobile DDR SDRAM). By using this feature, the system can cut off almost all DRAM power without adding the cost of
a power switch and giving up mother-board power-line layout flexibility.
All inputs are LVCMOS compatible. Devices will have a V
DD
and V
DDQ
supply of 1.8V (nominal).
The Hynix H5MS1222EFP series is available in the following package:
-
90Ball FBGA [size: 8mm x 13mm, t=1.0mm
max
]
128Mb Mobile DDR SDRAM ORDERING INFORMATION
Part Number
H5MS1222EFP-Q3E
H5MS1222EFP-J3E
H5MS1222EFP-K3E
H5MS1222EFP-L3E
Clock Frequency
185MHz(CL3) / 83MHz(CL2)
166MHz(CL3) / 83MHz(CL2)
133MHz(CL3) / 83MHz(CL2)
100MHz(CL3) / 66MHz(CL2)
4banks x 1Mb x 32
LVCMOS
Mobile Temp.
: -30
o
C
~
85
o
C
Extended
Temp. : -25
o
C
~ 85
o
C
90Ball Lead
Free
Organization
Interface
Temp.
Package
H5MS1222EFP-Q3M 185MHz(CL3) / 83MHz(CL2)
H5MS1222EFP-J3M
166MHz(CL3) / 83MHz(CL2)
H5MS1222EFP-K3M 133MHz(CL3) / 83MHz(CL2)
H5MS1222EFP-L3M
100MHz(CL3) / 66MHz(CL2)
90Ball Lead
Free
Rev 1.0 / Jun. 2008
5
