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H5PS5182GFR-C4L

DDR DRAM, 64MX8, 0.5ns, CMOS, PBGA60, HALOGEN FREE AND ROHS COMPLIANT, FBGA-60

器件类别:存储    存储   

厂商名称:SK Hynix(海力士)

厂商官网:http://www.hynix.com/eng/

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
SK Hynix(海力士)
零件包装代码
BGA
包装说明
TFBGA, BGA60,9X11,32
针数
60
Reach Compliance Code
unknow
ECCN代码
EAR99
访问模式
FOUR BANK PAGE BURST
最长访问时间
0.5 ns
其他特性
AUTO/SELF REFRESH
最大时钟频率 (fCLK)
267 MHz
I/O 类型
COMMON
交错的突发长度
4,8
JESD-30 代码
R-PBGA-B60
JESD-609代码
e1
长度
9.5 mm
内存密度
536870912 bi
内存集成电路类型
DDR DRAM
内存宽度
8
功能数量
1
端口数量
1
端子数量
60
字数
67108864 words
字数代码
64000000
工作模式
SYNCHRONOUS
最高工作温度
95 °C
最低工作温度
组织
64MX8
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
TFBGA
封装等效代码
BGA60,9X11,32
封装形状
RECTANGULAR
封装形式
GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度)
260
电源
1.8 V
认证状态
Not Qualified
刷新周期
8192
座面最大高度
1.2 mm
自我刷新
YES
连续突发长度
4,8
最大供电电压 (Vsup)
1.9 V
最小供电电压 (Vsup)
1.7 V
标称供电电压 (Vsup)
1.8 V
表面贴装
YES
技术
CMOS
温度等级
OTHER
端子面层
Tin/Silver/Copper (Sn/Ag/Cu)
端子形式
BALL
端子节距
0.8 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
20
宽度
7.5 mm
文档预览
H5PS518(6)2GFR Series
512Mb DDR2 SDRAM
H5PS5182GFR-xxC
H5PS5182GFR-xxI
H5PS5182GFR-xxL
H5PS5182GFR-xxJ
H5PS5162GFR-xxC
H5PS5162GFR-xxI
H5PS5162GFR-xxL
H5PS5162GFR-xxJ
This document is a general product description and is subject to change without notice. SK hynix Inc. does not assume any responsi-
bility for use of circuits described. No patent licenses are implied.
Rev. 1.8 / June. 2013
1
H5PS518(6)2GFR Series
Revision History
Rev.
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
History
Release
Updated IDD Specification
Added IDD6 Low Power Products
Corrected typo
Corrected typo
Merged with x8 series(H5PS5182GFR)
Corrected typo
Updated PKG information
Commercial Temperature Range update
Draft Date
Sep. 2010
Sep.2010
Nov.2010
Dec.2010
Feb.2011
Mar.2011
Sep.2011
June.2012
June. 2013
0
o
C ~ 85
o
C --> 0
o
C ~ 95
o
C
Remark
Rev.1.8 / June. 2013
2
H5PS518(6)2GFR Series
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Features
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev.1.8 / June. 2013
3
H5PS518(6)2GFR Series
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD ,VDDQ =1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 2, 3, 4, 5, 6 and 7 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4 / 8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 84ball FBGA(x16) : 7.5mm x 12.5mm
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Self-Refresh High Temperature Entry
• Partial Array Self Refresh support
• Average Refresh Cycle (Tcase
0
o
C~ 95
o
C)
-
7.8 µs at
0
o
C ~ 85
o
C
- 3.9
µs at 85
o
C ~ 95
o
C
Commercial Temperature(
0
o
C ~ 95
o
C)
Industrial Temperature(
-40
o
C ~ 95
o
C)
Rev.1.8 / June. 2013
4
H5PS518(6)2GFR Series
Ordering Information
Part No.
H5PS5182GFR-xx*C
H5PS5182GFR-xx*I
H5PS5182GFR-xx*L
64Mx8
Configura-
tion
Power Consumption
Normal Consumption
Normal Consumption
Low Power Consumption
(IDD6 Only)
Low Power Consumption
(IDD6 Only)
Normal Consumption
Normal Consumption
32Mx16
Low Power Consumption
(IDD6 Only)
Low Power Consumption
(IDD6 Only)
Operation Temp
Commercial
Industrial
Commercial
60 Ball
fBGA
Package
H5PS5182GFR-xx*J
H5PS5162GFR-xx*C
H5PS5162GFR-xx*I
H5PS5162GFR-xx*L
Industrial
Commercial
Industrial
Commercial
84 Ball
fBGA
H5PS5162GFR-xx*J
Note:
Industrial
-XX* is the speed bin, refer to the Operating Frequency table for complete part number.
-
SK hynix Inc. Halogen-free products are compliant to RoHS.
SK hynix Inc. supports Lead & Halogen free parts for each speed grade with same specification, except Lead free
materials.
We'll add "R" character after "F" for Lead & Halogen free products
Rev.1.8 / June. 2013
5
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