CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Internal Power Dissipation may limit Output Current below
±17mA.
2. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175
o
C for the ceramic package,
and below 150
o
C for the plastic package.
3.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
SUPPLY
=
±15V;
S/H Control V
IL
= +0.8V (Sample): V
IH
= +2.0V (Hold); SIG GND = SUPPLY GND,
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified
TEST
CONDITIONS
TEMP.
(
o
C)
HA-5330-2
MIN
TYP
MAX
MIN
HA-5330-5
TYP
MAX
UNITS
PARAMETER
INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance (Note 4)
Input Capacitance
Offset Voltage
Full
25
25
25
Full
±10
5
-
-
-
-
-
-
-
-
±10
86
-
15
3
0.2
-
1
±20
-
20
-
-
100
-
-
-
-
2.0
10
-
±500
-
500
-
-
±10
5
-
-
-
-
-
-
-
-
±10
86
-
15
3
0.2
-
1
±20
-
20
-
-
100
-
-
-
-
1.5
10
-
±300
-
300
-
-
V
MΩ
pF
mV
mV
µV/
o
C
nA
nA
nA
nA
V
dB
Offset Voltage Temperature Coefficient
Bias Current
Full
25
Full
Offset Current
25
Full
Common Mode Range
CMRR
TRANSFER CHARACTERISTICS
Gain
Gain Bandwidth Product
OUTPUT CHARACTERISTICS
Output Voltage
Output Current
Full Power Bandwidth (Note 6)
Output Resistance
Hold Mode
Sample Mode
DC
Note 12
V
CM
=
±10V
Full
Full
Full
25
2 x 10
6
-
2 x 10
7
4.5
-
-
2 x 10
6
-
2 x 10
7
4.5
-
-
V/V
MHz
Full
Full
25
25
25
±10
±10
-
-
-
-
-
1.4
0.2
10
-5
-
-
-
-
0.001
±10
±10
-
-
-
-
-
1.4
0.2
10
-5
-
-
-
-
0.001
V
mA
MHz
Ω
Ω
2
HA-5330
Electrical Specifications
V
SUPPLY
=
±15V;
S/H Control V
IL
= +0.8V (Sample): V
IH
= +2.0V (Hold); SIG GND = SUPPLY GND,
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
Sample Mode
Hold Mode
TRANSIENT RESPONSE
Rise Time
Overshoot
Slew Rate
DIGITAL INPUT CHARACTERISTICS
Input Voltage
V
IH
V
IL
Input Current
V
IL
= 0V
V
IH
= 5V
SAMPLE/HOLD CHARACTERISTICS
Acquisition Time
To 0.1%, Note 8
25
Full
To 0.01%, Note 8
25
Full
Aperture Time (Note 4)
Effective Aperture Delay Time
Aperture Uncertainty
Droop Rate (Note 9)
25
25
25
25
Full
Hold Step Error
Hold Mode Settling Time
Hold Mode Feedthrough
POWER SUPPLY CHARACTERISTICS
Positive Supply Current
Negative Supply Current
Power Supply Rejection
NOTES:
4. Derived from computer simulation only; not tested.
Slew Rate
6. Full power bandwidth based on slew rate measurement using: FPBW
= ---------------------------
. Distortion of wave shape occurs beyond 100kHz due to
2πV PEAK
slew rate enhancement circuitry.
7. V
O
= 20V Step; R
L
= 2kΩ; C
L
= 50pF.
8. V
O
= 10V Step; R
L
= 2kΩ; C
L
= 50pF.
9. This parameter is measured at ambient temperature extremes in a high speed test environment. Consequently, steady state heating effects from
internal power dissipation are not included.
10. V
IN
= 0V; V
IH
= +3.5V; t
R
= 22ns (V
IL
to V
IH
). See graph.
11. Based on a 3V delta in each supply, i.e. 15V
±1.5V
DC
.
12. V
OUT
= 200mV
P-P
, R
L
= 2kΩ, C
L
= 50pF.
5. V
I
= 200mV Step; R
L
= 2kΩ; C
L
= 50pF.
Note 11
Full
Full
Full
-
-
86
18
19
100
22
23
-
-
-
86
18
19
100
24
25
-
mA
mA
dB
Note 10
To 0.01%
20V
P-P
, 100kHz
25
25
Full
-
-
-
-
-
-50
-
-
-
-
-
-
500
-
650
-
20
-25
0.1
0.01
-
0.5
100
-88
-
700
-
900
-
0
-
-
100
-
200
-
-
-
-
-
-
-50
-
-
-
-
-
-
500
-
650
-
20
-25
0.1
0.01
-
0.5
100
-88
-
700
-
900
-
0
-
-
10
-
200
-
ns
ns
ns
ns
ns
ns
ns
µV/µs
µV/µs
mV
ns
dB
Full
Full
Full
Full
2.0
-
-
-
-
-
10
10
-
0.8
40
40
2.0
-
-
-
-
-
10
10
-
0.8
40
40
V
V
µA
µA
Note 5
Note 5
Note 7
25
25
25
-
-
-
70
10
90
-
-
-
-
-
-
70
10
90
-
-
-
ns
%
V/µs
25
TEMP.
(
o
C)
HA-5330-2
MIN
-
-
TYP
230
190
MAX
-
-
MIN
-
-
HA-5330-5
TYP
230
190
MAX
-
-
UNITS
µV
RMS
µV
RMS
PARAMETER
Total Output Noise, DC to 4MHz
3
HA-5330
Application Information
The HA-5330 has the uncommitted differential inputs of an
op amp, allowing the Sample/Hold function to be combined
with many conventional op amp circuit ideas. See the Intersil
Application Note AN517 for a collection of circuit ideas.
Output Stage
The HA-5330 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load
current which occur during an A/D conversion are absorbed
at the S/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.
Layout
A printed circuit board with ground plane is recommended
for best performance. Bypass capacitors (0.01µF to 0.1µF,
ceramic) should be provided from each power supply
terminal to the Supply GND Terminal on pin 11.
Glossary of Terms
Acquisition Time
The time required following a “sample” command, for the
output to reach its final value within
±0.1%
or
±0.01%.
This is
the minimum sample time required to obtain a given
accuracy, and includes switch delay time, slewing time and
settling time.
Typical Applications
The HA-5330 is configured as a unity gain noninverting
amplifier by simply connecting the output (pin 7) to the
inverting input (pin 14). As an input device for a fast
successive - approximation A/D converter, it offers an
extremely high throughput rate. Also, the HA-5330’s
pedestal error is adjustable to zero by using an Offset Adjust
potentiometer (10K to 50K) center tapped to V-.
V-
10kΩ - 50kΩ
3
4
Aperture Time
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is that interval
between the conditions of 10% open and 90% open.
Hold Step Error
Hold step error is the output shift due to charge transfer from
the sample to the hold mode. It is also referred to as “offset
step” or “pedestal error”.
3.0
2.0
1.0
0.0
-1.0
-2.0
20
40
60
80
100
RISE TIME (ns) 0V TO 3.5V
The ideal ground connections are pin 11 (Supply Ground)
directly to the system Supply Common, and pin 12 (Signal
Ground) directly to the system Signal Ground (Analog
Ground).
Hold Capacitor
The HA-5330 includes a 90pF MOS hold capacitor, sufficient
for most high speed applications (the Electrical
Specifications section is based on the internal capacitor).
MAGNITUDE
40
Effective Aperture Delay Time (EADT)
The difference between the digital delay time from the Hold
command to the opening of the S/H switch, and the
propagation time from the analog input to the switch.
EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to V
IN
at the instant the
Hold command was received. For negative EADT, the output
in Hold (exclusive of pedestal and droop errors) will
correspond to a value of V
IN
that occurred before the Hold
command.
PHASE
0
±15V
SUPPLIES
-20
90
0
-40
1K
10K
100K
±12V
SUPPLIES
1M
180
10M
PHASE (DEGREES)
MAGNITUDE (dB)
20
Aperture Uncertainty
The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay Uncertainty,
Aperture Time Jitter, etc.) sets a limit on the accuracy with
which a waveform can be reconstructed from sample data.
FREQUENCY (Hz)
FIGURE 2. MAGNITUDE AND PHASE RESPONSE
(CLOSED LOOP GAIN = 100)
4
HOLD STEP ERROR (mV)
FIGURE 1. HA-5330 OFFSET ADJUST
FIGURE 3. HOLD STEP ERROR vs S/H CONTROL RISE TIME
HA-5330
Die Characteristics
DIE DIMENSIONS:
99 mils x 166 mils x 19 mils
2510µm x 4210µm x 483µm
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16k
Å
±2k
Å
PASSIVATION:
Type: Nitride (Si
3
N
4
) over Silox (SiO
2
, 5% Phos.)
Silox Thickness: 12k
Å
±2k
Å
Nitride Thickness: 3.5k
Å
±1.5k
Å
SUBSTRATE POTENTIAL (Powered Up):
Signal GND
TRANSISTOR COUNT:
205
PROCESS:
Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5330
+IN
-IN
SIGNAL GND
SUPPLY GND
V+
OFFSET ADJ
OFFSET ADJ
V-
OUTPUT
S/H CONTROL
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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