PRELIMINARY DATA SHEET
256MB DDR SDRAM S.O.DIMM
HB54A2568KN-A75B/B75B/10B
(32M words
×
64 bits, 2 Banks)
Description
The HB54A2568KN is Double Data Rate (DDR)
SDRAM Module, mounted 256M bits DDR SDRAM
(HM5425161BTT) sealed in TSOP package, and 1
piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD).
The HB54A2568KN is
organized as 16M
×
64
×
2 bank mounted 8 pieces of
256M bits DDR SDRAM. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. An outline of the products is
200-pin socket type package (dual lead out).
Therefore, it makes high density mounting possible
without surface mount technology. It provides common
data inputs and outputs. Decoupling capacitors are
mounted beside each TSOP on the module board.
Features
•
200-pin socket type package (dual lead out)
Outline: 67.6mm (Length)
×
31.75mm (Height)
×
3.80mm (Thickness)
Lead pitch: 0.6mm
•
2.5V power supply (VCC)
•
SSTL-2 interface for all inputs and outputs
•
Clock frequency: 133 MHz (max) (-A75B/B75B)
: 100 MHz (max) (-10B)
•
Data inputs, outputs and DM are synchronized with
DQS
•
4 banks can operate simultaneously and
independently (Component)
•
Burst read/write operation
•
Programmable burst length: 2, 4, 8
Burst read stop capability
•
Programmable burst sequence
Sequential
Interleave
•
Start addressing capability
Even and Odd
•
Programmable /CAS latency (CL): 2, 2.5
•
8192 refresh cycles: 7.8µs (8192row /64ms)
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0148H20 (Ver. 2.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2001-2002
Hitachi,
Ltd. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB54A2568KN-A75B/B75B/10B
Ordering Information
Part number
HB54A2568KN-A75B*
HB54A2568KN-B75B*
2
HB54A2568KN-10B*
3
1
Clock frequency
MHz (max.)
133 MHz
133 MHz
100 MHz
/CAS latency
2.0
2.5
2.0
Package
Contact pad
200-pin dual lead out socket Gold
type
Notes: 1. 143 MHz operation at /CAS latency = 2.5.
2. 100 MHz operation at /CAS latency = 2.0.
3. 125 MHz operation at /CAS latency = 2.5.
Pin Configurations
Front side
1 pin
39 pin 41 pin
199 pin
2 pin
40 pin 42 pin
Back side
200 pin
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Pin name
VREF
VSS
DQ0
DQ1
VCC
DQS0
DQ2
VSS
DQ3
DQ8
VCC
DQ9
DQS1
VSS
DQ10
DQ11
VCC
CK0
/CK0
VSS
DQ16
DQ17
VCC
DQS2
DQ18
Pin No.
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Pin name
VSS
DQ19
DQ24
VCC
DQ25
DQS3
VSS
DQ26
DQ27
VCC
NC
NC
VSS
NC
NC
VCC
NC
NC
VSS
CK2
/CK2
VCC
CKE1
NC
A12
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Pin name
VREF
VSS
DQ4
DQ5
VCC
DM0
DQ6
VSS
DQ7
DQ12
VCC
DQ13
DM1
VSS
DQ14
DQ15
VCC
VCC
VSS
VSS
DQ20
DQ21
VCC
DM2
DQ22
Pin No.
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Pin name
VSS
DQ23
DQ28
VCC
DQ29
DM3
VSS
DQ30
DQ31
VCC
NC
NC
VSS
NC
NC
VCC
NC
NC
VSS
VSS
VCC
VCC
CKE0
NC
A11
Preliminary Data Sheet E0148H20 (Ver. 2.0)
2
HB54A2568KN-A75B/B75B/10B
Pin No.
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Pin name
A9
VSS
A7
A5
A3
A1
VCC
A10/AP
BA0
/WE
/S0
NC
VSS
DQ32
DQ33
VCC
DQS4
DQ34
VSS
DQ35
DQ40
VCC
DQ41
DQS5
VSS
Pin No.
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Pin name
DQ42
DQ43
VCC
VCC
VSS
VSS
DQ48
DQ49
VCC
DQS6
DQ50
VSS
DQ51
DQ56
VCC
DQ57
DQS7
VSS
DQ58
DQ59
VCC
SDA
SCL
VCCSPD
VCCID
Pin No.
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Pin name
A8
VSS
A6
A4
A2
A0
VCC
BA1
/RAS
/CAS
/S1
NC
VSS
DQ36
DQ37
VCC
DM4
DQ38
VSS
DQ39
DQ44
VCC
DQ45
DM5
VSS
Pin No.
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Pin name
DQ46
DQ47
VCC
/CK1
CK1
VSS
DQ52
DQ53
VCC
DM6
DQ54
VSS
DQ55
DQ60
VCC
DQ61
DM7
VSS
DQ62
DQ63
VCC
SA0
SA1
SA2
NC
Preliminary Data Sheet E0148H20 (Ver. 2.0)
3
HB54A2568KN-A75B/B75B/10B
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
/RAS
/CAS
/WE
/S0, /S1
CKE0, CKE1
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS7
DM0 to DM7
SCL
SDA
SA0 to SA2
VCC
VCCSPD
VREF
VSS
VCCID
NC
Function
Address input
Row address
Column address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
VCC identification flag
No connection
A0 to A12
A0 to A8
Bank select address
Preliminary Data Sheet E0148H20 (Ver. 2.0)
4
HB54A2568KN-A75B/B75B/10B
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
6
7
8
9
1
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM banks
Module data width
Module data width continuation
DDR SDRAM cycle time, CL = X
-A75B
-B75B
-10B
SDRAM access from clock (tAC)
-A75B/B75B
-10B
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at
CLX - 0.5
-A75B
-B75B/10B
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
Bit5 Bit4
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
Bit3
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
Bit2
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
Bit1 Bit0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
Hex value
80
08
07
0D
09
02
40
00
04
70
75
80
70
80
00
82
10
00
01
0E
04
0C
01
02
20
80
75
A0
70
80
00
00
50
Comments
128
256 byte
SDRAM DDR
13
9
2
64 bits
0 (+)
SSTL 2.5V
CL = 2.5*
5
Voltage interface level of this assembly 0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
10
0.7ns*
5
0.8ns*
5
Non-parity
7.8 µs
Self refresh
×
16
Not used
1 CLK
2, 4, 8
4
2, 2.5
0
1
Unbuffered
± 0.2V
CL = 2*
5
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Maximum data access time (tAC) from
0
clock at CLX - 0.5
-A75B/B75B
-10B
1
Minimum clock cycle time at
0
CLX - 1
Maximum data access time (tAC) from
0
clock at CLX - 1
Minimum row precharge time (tRP)
0
0.7ns*
5
0.8ns*
5
25
26
27
20ns
Preliminary Data Sheet E0148H20 (Ver. 2.0)
5
