SL74HC109
Dual J -K Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The SL74HC109 is identical in pinout to the LS/ALS109. The device
inputs are compatible with standard CMOS outputs, with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs
with the next low-to-high transition of the clock. Both Q to Q outputs
are available from each flip-flop.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µ
A
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC109N Plastic
SL74HC109D SOIC
T
A
= -55
°
to 125
°
C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
H
PIN 16=V
CC
PIN 8 = GND
H
Reset
H
L
L
H
H
H
H
H
L
Clock
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Outputs
Q
H
L
H
*
Q
L
H
H
*
L
H
Toggle
No Change
H
L
No Change
X = Don’t care
*
Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
SLS
System Logic
Semiconductor
SL74HC109
MAXIMUM RATINGS
*
Symbol
V
CC
V
I N
V
O U T
I
I N
I
O U T
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±
20
±
25
±
50
Unit
V
V
V
mA
mA
mA
mW
°
C
°
C
750
500
-65 to +150
260
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
°
C from 65
°
to 125
°
C
SOIC Package: : - 7 mW/
°
C from 65
°
to 125
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I N
, V
O U T
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°
C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
I N
and V
O U T
should be constrained to the range
GND
≤
(V
I N
or V
O U T
)
≤
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC109
D C E L E C T R I C A L C H A R A C T E R I S T I C S
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°
C
to
-55
°
C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
0.1
≤
85
°
C
≤
125
°
C
Unit
V
I H
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
O U T
=0.1 V or V
CC
-0.1 V
I
O U T
≤
20
µ
A
V
O U T
=0.1 V or V
CC
-0.1 V
I
O U T
≤
20
µ
A
V
I N
=V
I H
or V
IL
I
O U T
≤
20
µ
A
V
I N
=V
I H
or V
IL
I
O U T
≤
4.0 mA
I
O U T
≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
1.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
1.0
V
V
IL
V
V
O H
V
V
O L
Maximum Low-Level
Output Voltage
V
I N
= V
IL
or V
I H
I
O U T
≤
20
µ
A
V
I N
= V
IL
or V
I H
I
O U T
≤
4.0 mA
I
O U T
≤
5.2 mA
V
I
I N
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V
I N
=V
CC
or GND
V
I N
=V
CC
or GND
I
O U T
=0
µ
A
µ
A
µ
A
4.0
40
80
SLS
System Logic
Semiconductor
SL74HC109
A C E L E C T R I C A L C H A R A C T E R I S T I C S
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
m a x
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
Maximum Propagation Delay , Set or Reset to Q or
Q (Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Flip-Flop)
C
P D
Used to determine the no-load dynamic power
2
consumption: P
D
=C
P D
V
CC
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°
C to
-55
°
C
6
30
35
175
35
30
230
46
39
75
15
13
10
≤
85
°
C
≤
125
°
C
Unit
MHz
4.8
24
28
220
44
37
290
58
49
95
19
16
10
4.0
20
24
265
53
45
345
69
59
110
22
19
10
t
P L H
, t
P H L
ns
t
P L H
, t
P H L
ns
t
T L H
, t
T H L
ns
C
I N
pF
Typical @25
°
C,V
CC
=5.0 V
40
pF
T I M I N G R E Q U I R E M E N T S
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
SU
Parameter
Minimum Setup Time, J or K to
Clock (Figure 3)
Minimum Hold Time, Clock to
J or K (Figure 3)
Minimum Recovery Time, Set
or Reset Inactive to Clock
(Figure 2)
Minimum Pulse Width, Set or
Reset (Figure 2)
Minimum Pulse Width,Clock
(Figure 1)
Maximum Input Rise and Fall
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25
°
C to -55
°
C
100
20
17
5
5
5
5
5
5
80
16
14
80
16
14
1000
500
400
≤
85
°
C
≤
125
°
C
Unit
ns
125
25
21
5
5
5
5
5
5
100
20
17
100
20
17
1000
500
400
150
30
26
5
5
5
5
5
5
12
24
20
12
24
20
1000
500
400
t
h
ns
t
r e c
ns
t
w
ns
t
w
ns
t
r,
t
f
ns
SLS
System Logic
Semiconductor
SL74HC109
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
SLS
System Logic
Semiconductor
