HCC/HCF4536B
PROGRAMMABLE TIMER
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24 FLIP-FLOP STAGES - COUNTS FROM
2
0
TO 2
24
LAST 16 STAGES SELECTABLE BY BCD SE-
LECT CODE
BYPASS INPUT ALLOWS BYPASSING FIRST
8 STAGES
ON-CHIP RC OSCILLATOR PROVISION
CLOCK INHIBIT INPUT
SCHMITT-TRIGGER IN CLOCK LINE PER-
MITS OPERATION WITH VERY LONG RISE
AND FALL TIMES
ON-CHIP MONOSTABLE OUTPUT PROVI-
SION
TYPICAL f
CL
= 3MHz AT V
DD
= 10V
TEST MODE ALLOWS FAST TEST SE-
QUENCE
SET AND RESET INPUTS
CAPABLE OF DRIVING TWO LOW POWER
TTL
LOADS,
ONE
LOWER-POWER
SCHOTTKY LOAD, OR TWO HTL LOADS
OVER THE RATED TEMPERATURE RANGE
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT AT 20V FOR HCC DE-
VICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100 nA AT 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
o
TATIVE STANDARD N . 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4536BF
HCF4536BEY
HCF4536BC1
PIN CONNECTIONS
DESCRIPTION
The
HCC4536B
(extended temperature range) and
HCF4536B
(intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package. The
HCC/HCF4536B
is a programmable timer consi-
sting of 24 ripple-binary counter stages. The salient
feature of this device is its flexibility. The device can
count from 1 to 2
24
or the first 8 stages can be by-
passed to allow an output, selectable by a 4-bit co-
de, from any one of the remaining 16 stages. It can
be driven by an external clock or an RC oscillator
that can be constructed using on-chip components.
November 1996
1/17
HCC/HCF4536B
Input IN1 serves as either the external clock input or
the input to the on-chip RC oscillator. OUT1 and
OUT2 are connection terminals for the external RC
components. In addition, an on-chip monostable cir-
cuit is provided to allow a variable pulse width out-
put. Various timing functions can be achieved using
combinations of these capabilities. A logic 1 on the
8-BYPASS input enables a bypass of the first 8 sta-
ges and makes stage 9 the first counter stage of the
last 16 stages. Selection of 1 of 16 outputs is accom-
plished by the decoder and the BCD inputs A, B, C
FUNCTIONAL DIAGRAM
and D. MONO IN is the timing input for the on-chip
monostable oscillator. Grounding of the MONO IN
terminal through a resistor of 10KΩ or higher, disa-
bles the one-shot circuit and connects the decoder
directly to the DECODE OUT terminal. A resistor to
V
DD
and a capacitor to ground from the MONO IN
terminal enables the one-shot circuit and controls its
pulse width. A fast test mode is enabled by a logic
1 on 8-BYPASS, SET, and RESET. This mode di-
vides the 24-stage counter into three 8-stage sec-
tions to facilitate a fast test sequence.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
*
V
i
I
I
P
t ot
Parameter
Supply Voltage :
H CC
Types
H C F
Types
Input Voltage
DC Input Current (any one input)
Total Power Dissipation (per package)
Dissipation per Output Transistor
for T
o p
= Full Package-temperature Range
Operating Temperature :
H CC
Types
H C F
Types
Storage Temperature
Value
– 0.5 to + 20
– 0.5 to + 18
– 0.5 to V
DD
+ 0.5
±
10
200
100
– 55 to + 125
– 40 to + 85
– 65 to + 150
Unit
V
V
V
mA
mW
mW
°C
°C
°C
T
op
T
stg
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltages are with respect to V
SS
(GND).
2/17
HCC/HCF4536B
BLOCK DIAGRAM
TRUTH TABLE
In 1 Set Reset Clock Osc Out1 Out2 Decode
Inh Inh
Out
–
–/
–\
–
X
X
X
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
X
–
–/
0
–\
–
1
–
–/
–\
–
0
0
–\
–
No
Change
DECODE OUT SELECTION TABLE
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Number or Stages
I n Divider Chain
8-BYPASS = 0 8-BYPASS = 1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Advance
/– to Next
–
State
1
1
1
0
No
Change
No
Change
Advance
/– to Next
–
State
0 = Low Level
0 = Low Level
3/17
HCC/HCF4536B
LOGIC DIAGRAMS
(continued on next page)
4/17
HCC/HCF4536B
LOGIC DIAGRAMS
(continued)
5/17
分立器件
